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CMSIS_5-develop/CMSIS/DoxyGen/Core_A/core_A.dxy Normal file
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/** \page coreMISRA_Exceptions_pg MISRA-C Deviations
CMSIS-Core (Cortex-A) uses the common coding rules for CMSIS components that are documented under
<a href="../../General/html/index.html"><b>Introduction</b></a>.
CMSIS-Core (Cortex-A) violates the following MISRA-C:2004 rules:
TO BE EVALUATED
*/
/*
- Required Rule 8.5, object/function definition in header file.<br>
Violated since function definitions in header files are used for function inlining'.
- Advisory Rule 12.4, Side effects on right hand side of logical operator.<br>
Violated because volatile is used for core register definitions.
- Advisory Rule 14.7, Return statement before end of function.<br>
Violated to simplify code logic.
- Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Violated since unions are used for effective representation of core registers.
- Advisory Rule 19.4, Disallowed definition for macro.<br>
Violated since macros are used for assembler keywords.
- Advisory Rule 19.7, Function-like macro defined.<br>
Violated since function-like macros are used to generate more efficient code.
- Advisory Rule 19.16, all preprocessing directives must be valid.<br>
Violated to set default settings for macros.
*/
/**
CMSIS-Core (Cortex-A) violates the following MISRA-C:2012 rules:
TO BE EVALUATED
*/
/*
- Directive 4.9, function-like macro defined.<br>
Violated since function-like macros are used to generate more efficient code.
- Rule 1.3, multiple use of '#/##' operators in macro definition.<br>
Violated since function-like macros are used to generate more efficient code.
- Rule 11.4, conversion between a pointer and integer type.<br>
Violated because of core register access.
- Rule 11.6, cast from unsigned long to pointer.<br>
Violated because of core register access.
- Rule 13.5, side effects on right hand side of logical operator.<br>
Violated because of shift operand is used in macros and functions.
- Rule 14.4, conditional expression should have essentially Boolean type.<br>
Violated since macros with several instructions are used.
- Rule 15.5, return statement before end of function.<br>
Violated to simplify code logic.
- Rule 20.10, '#/##' operators used.<br>
Violated since function-like macros are used to generate more efficient code.
- Rule 21.1, reserved to the compiler.<br>
Violated since macros with leading underscores are used.
*/

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/** \mainpage Overview
CMSIS-Core (Cortex-A) implements the basic run-time system for a Cortex-A device and gives the user access to the processor core and the device peripherals.
In detail it defines:
- <b>Hardware Abstraction Layer (HAL)</b> for Cortex-A processor registers with standardized definitions for the GIC, FPU, MMU, Cache, and core access functions.
- <b>System exception names</b> to interface to system exceptions without having compatibility issues.
- <b>Methods to organize header files</b> that makes it easy to learn new Cortex-A microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
- <b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
- <b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.
- A variable to determine the <b>system clock frequency</b> which simplifies the setup of the system timers.
The following sections provide details about the CMSIS-Core (Cortex-A):
- \ref using_pg describes the project setup and shows a simple program example.
- \ref templates_pg describes the files of the CMSIS-Core (Cortex-A) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
- \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
- <a href="modules.html">\b Reference </a> describe the features and functions of the \ref device_h_pg in detail.
- <a href="annotated.html">\b Data \b Structures </a> describe the data structures of the \ref device_h_pg in detail.
<hr>
CMSIS-Core (Cortex-A) in ARM::CMSIS Pack
-----------------------------
Files relevant to CMSIS-Core (Cortex-A) are present in the following <b>ARM::CMSIS</b> directories:
|File/Folder |Content |
|--------------------------------|------------------------------------------------------------------------|
|\b CMSIS\\Documentation\\Core_A | This documentation |
|\b CMSIS\\Core_A\\Include | CMSIS-Core (Cortex-A) header files (for example core_ca.h, etc.) |
|\b Device | \ref using_ARM_pg "Arm reference implementations" of Cortex-A devices |
|\b Device\\\_Template_Vendor | \ref templates_pg for extension by silicon vendors |
<hr>
\section ref_v7A Processor Support
CMSIS supports a selected subset of <a href="http://www.arm.com/products/processors/cortex-a/index.php" target="_blank"><b>Cortex-A processors</b></a>.
\subsection ref_man_ca_sec Cortex-A Technical Reference Manuals
The following Technical Reference Manuals describe the various Arm Cortex-A processors:
- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/DDI0433C_cortex_a5_trm.pdf" target="_blank"><b>Cortex-A5</b></a> (Armv7-A architecture)
- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf" target="_blank"><b>Cortex-A7</b></a> (Armv7-A architecture)
- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/arm_cortexa9_trm_100511_0401_10_en.pdf" target="_blank"><b>Cortex-A9</b></a> (Armv7-A architecture)
<hr>
\section tested_tools_sec Tested and Verified Toolchains
The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
- Arm: Arm Compiler 5.06 update 7
- Arm: Arm Compiler 6.16
- Arm: Arm Compiler 6.6.4
- GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)
- IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
<hr>
*/
/**
\page rev_histCoreA Revision History of CMSIS-Core (Cortex-A)
<table class="cmtable" summary="Revision History">
<tr>
<th>Version</th>
<th>Description</th>
</tr>
<tr>
<td>V1.2.1</td>
<td>
<ul>
<li>Bugfixes for Cortex-A32</li>
</ul>
</td>
</tr>
<tr>
<td>V1.2.0</td>
<td>
<ul>
<li>Fixed GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR
for compliance with all GIC specification versions.</li>
<li>Added missing DSP intrinsics.</li>
<li>Reworked assembly intrinsics: volatile, barriers and clobbers.</li>
</ul>
</td>
</tr>
<tr>
<td>V1.1.4</td>
<td>
<ul>
<li>Fixed __FPU_Enable().</li>
</ul>
</td>
</tr>
<tr>
<td>V1.1.3</td>
<td>
<ul>
<li>Fixed __get_SP_usr()/__set_SP_usr() for ArmClang.</li>
<li>Fixed zero argument handling in __CLZ() .</li>
</ul>
</td>
</tr>
<tr>
<td>V1.1.2</td>
<td>
<ul>
<li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>
<li>Fixed co-processor register access macros for Arm Compiler 5.</li>
</ul>
</td>
</tr>
<tr>
<td>V1.1.1</td>
<td>
<ul>
<li>Refactored L1 cache maintenance to be compiler agnostic.</li>
</ul>
</td>
</tr>
<tr>
<td>V1.1.0</td>
<td>
<ul>
<li>Added compiler_iccarm.h for IAR compiler.</li>
<li>Added missing core access functions for Arm Compiler 5.</li>
<li>Aligned access function to coprocessor 15.</li>
<li>Additional generic Timer functions.</li>
<li>Bug fixes and minor enhancements.</li>
</ul>
</td>
</tr>
<tr>
<td>V1.0.0</td>
<td>Initial Release for Cortex-A5/A7/A9 processors.</td>
</tr>
</table>
*/
/**
\page device_h_pg Device Header File \<device.h>
The \ref device_h_pg contains the following sections that are device specific:
- \ref irqn_defs provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
- \ref config_perifs reflect the features of the device.
- \ref access_perifs definitions for the \ref peripheral_gr to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
- <b>Access Functions for Peripherals (optioal)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
\section irqn_defs Interrupt Number Definition
\section config_perifs Configuration of the Processor and Core Peripherals
\section access_perifs Device Peripheral Access Layer
*/

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/* ################################ System and Clock Configuration ########################### */
/**************************************************************************************************/
/**
\defgroup system_init_gr System and Clock Configuration
\brief Functions for system and clock setup available in system_<i>device</i>.c.
\details
Arm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by
the silicon vendor to match their actual device. As a <b>minimum requirement</b>,
this file must provide:
- A device-specific system configuration function, \ref SystemInit().
- A global variable that contains the system frequency, \ref SystemCoreClock.
The file configures the device and, typically, initializes the oscillator (PLL) that is part
of the microcontroller device. This file might export other functions or variables that provide
a more flexible configuration of the microcontroller system.
\note Please pay special attention to the static variable \c SystemCoreClock. This variable might be
used throughout the whole system initialization and runtime to calculate frequency/time related values.
Thus one must assure that the variable always reflects the actual system clock speed. Be aware that
a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get
overwritten by C library startup code. Thus its highly recommended to call \ref SystemCoreClockUpdate
at the beginning of the user \c main() routine.
\section system_init_code_ex_sec Code Example
The code below shows the usage of the variable \ref SystemCoreClock and the functions
SystemInit() and SystemCoreClockUpdate() with an arbitrary Arm Cortex-A9.
\code
#include "ARMCA9.h"
uint32_t coreClock_1 = 0; /* Variables to store core clock values */
uint32_t coreClock_2 = 0;
int main (void) {
coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */
SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */
coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */
if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */
// Error Handling
}
while(1);
}
\endcode
@{
*/
/**************************************************************************************************/
/**
\brief Variable to hold the system core clock value
\details
Holds the system core clock, which is the system clock frequency supplied to the SysTick
timer and the processor core clock. This variable can be used by debuggers to query the
frequency of the debug timer or to configure the trace clock speed.
\attention Compilers must be configured to avoid removing this variable in case the application
program is not using it. Debugging systems require the variable to be physically
present in memory so that it can be examined to configure the debugger.
*/
uint32_t SystemCoreClock;
/**************************************************************************************************/
/**
\brief Function to Initialize the system.
\details
Initializes the microcontroller system. Typically, this function configures the
oscillator (PLL) that is part of the microcontroller device. For systems
with a variable clock speed, it updates the variable \ref SystemCoreClock.
SystemInit is called from the file <b>startup<i>_device</i></b>.
*/
void SystemInit (void);
/**************************************************************************************************/
/**
\brief Function to update the variable \ref SystemCoreClock
\details
Updates the variable \ref SystemCoreClock and must be called whenever the core clock is changed
during program execution. The function evaluates the clock register settings and calculates
the current core clock.
*/
void SystemCoreClockUpdate (void);
/** @} */ /* end group system_init_gr */

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/**
\page templates_pg CMSIS-Core Device Templates
\details
Arm supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors.
Refer to the list of \ref tested_tools_sec for compliance.
These CMSIS-Core device template files include the following:
- Register names of the Core Peripherals and names of the Core Exception Vectors.
- Functions to access core peripherals, cache, MMU and special CPU instructions
- Generic startup code and system configuration code.
The detailed file structure of the CMSIS-Core device templates is shown in the following picture.
<!-- \image html "CMSIS_CORE_Files.png" "CMSIS-Core File Structure" -->
\section CMSIS_Processor_files CMSIS-Core Processor Files
The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core_A\\Include. These header files define all processor specific attributes do not need any modifications.
The <b>core_&lt;cpu&gt;.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-A processor:
Header File | Processor
:----------------|:------------------------------
core_ca.h | generics for all supported Cortex-A processors
\section device_examples Device Examples
The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\\Device\\ARM
and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:
Family | Device | Description
:------------------|:------------------|:---------------------------------
ARM Cortex-A5 | ARMCA5 | Cortex-A5 based device
ARM Cortex-A7 | ARMCA7 | Cortex-A7 based device
ARM Cortex-A9 | ARMCA9 | Cortex-A9 based device
\section template_files_sec Template Files
To simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals.
Silicon vendors add to these template files the following information:
- <b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.
- <b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.
- <b>Interrupt vectors</b> in the startup file that are device specific.
<table class="cmtable">
<tr>
<th>Template File</th>
<th>Description</th>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\startup_Device.c</td>
<td>Startup file template for Arm C/C++ Compiler.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\Device.sct</td>
<td>Linker scatter file template for Arm C/C++ Compiler.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\system_Device.c</td>
<td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\mmu_Device.c</td>
<td>Sample mmu_Device.c file with memory map description for Memory Management Unit (MMU) configuration.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Include\\Device.h</td>
<td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals
can be part of that file.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Include\\system_Device.h</td>
<td>Generic system device configuration include file.</td>
</tr>
<tr>
<td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Include\\mem_Device.h</td>
<td>Generic memory base address and size definitions used in scatter file. Settable via Configuration Wizard.</td>
</tr>
</table>
<b>Adapt Template Files to a Device</b>
The following steps describe how to adopt the template files to a specific device or device family.
Copy the complete all files in the template directory and replace:
- directory name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
- directory name 'Device' with the specific device name e.g.: LPC17xx.
- in the file names 'Device' with the specific device name e.g.: LPC17xx.
Each template file contains comments that start with \b ToDo: that describe a required modification.
The template files contain place holders:
<table class="cmtable">
<tr>
<th>Placeholder</th>
<th>Replaced with</th>
</tr>
<tr>
<td>&lt;Device&gt;</td>
<td>the specific device name or device family name; i.e. LPC17xx.</td>
</tr>
<tr>
<td>&lt;DeviceInterrupt&gt;</td>
<td>a specific interrupt name of the device; i.e. TIM1 for Timer 1.</td>
<tr>
<td>&lt;DeviceAbbreviation&gt;</td>
<td>short name or abbreviation of the device family; i.e. LPC.</td>
</tr>
<tr>
<td>Cortex-M#</td>
<td>the specific Cortex-M processor name; i.e. Cortex-M3.</td>
</tr>
</table>
The device configuration of the template files is described in detail on the following pages:
- \subpage startup_c_pg
- \subpage system_c_pg
- \subpage device_h_pg
- \subpage mem_h_pg
- \subpage mmu_c_pg
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\page startup_c_pg Startup File startup_<device>.c
The \ref startup_c_pg contains:
- Exception vectors of the Cortex-A Processor with weak functions that implement default routines.
- The reset handler which is executed after CPU reset and typically calls the \ref SystemInit function.
- The setup values for the various stack pointers, i.e. per exceptional mode and main stack.
The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.
\section startup_c_sec startup_Device.c Template File
An Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below.
The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.
\verbinclude "Source/ARM/startup_Device.c"
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\page system_c_pg System Configuration Files system_<device>.c and system_<device>.h
The \ref system_c_pg provides as a minimum the functions described under \ref system_init_gr.
These functions are device specific and need adaptations. In addition, the file might have
configuration settings for the device such as XTAL frequency or PLL prescaler settings.
For devices with external memory BUS the system_<device>.c also configures the BUS system.
The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file.
In case of additional features the function prototypes need to be added to the system_<device>.h header file.
\section system_Device_sec system_Device.c Template File
The \ref system_Device_sec for the Cortex-M3 is shown below.
\verbinclude "Source/system_Device.c"
\section system_Device_h_sec system_Device.h Template File
The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file.
The \ref system_Device_h_sec is shown below.
\verbinclude "Include/system_Device.h"
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\page device_h_pg Device Header File \<device.h>
The \ref device_h_pg contains the following sections that are device specific:
- \ref irqn_defs provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
- \ref config_perifs reflect the features of the device.
- \ref access_perifs definitions for the \ref peripheral_gr to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
- <b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
<a href="modules.html">\b Reference </a> describes the standard features and functions of the \ref device_h_pg in detail.
\section interrupt_number_sec Interrupt Number Definition
\ref device_h_pg contains the enumeration \ref IRQn_Type that defines all exceptions and interrupts of the device.
For devices implementing an Arm GIC these are defined as:
- IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.
- IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.
- IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.
- IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.
\b Example:
The following example shows the extension of the interrupt vector table for Cortex-A9 class device.
\code
typedef enum IRQn
{
/****** SGI Interrupts Numbers ****************************************/
SGI0_IRQn = 0,
SGI1_IRQn = 1,
SGI2_IRQn = 2,
: :
SGI15_IRQn = 15,
/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
GlobalTimer_IRQn = 27, /*!< Global Timer Interrupt */
PrivTimer_IRQn = 29, /*!< Private Timer Interrupt */
PrivWatchdog_IRQn = 30, /*!< Private Watchdog Interrupt */
/****** Platform Exceptions Numbers ***************************************************/
Watchdog_IRQn = 32, /*!< SP805 Interrupt */
Timer0_IRQn = 34, /*!< SP804 Interrupt */
Timer1_IRQn = 35, /*!< SP804 Interrupt */
RTClock_IRQn = 36, /*!< PL031 Interrupt */
UART0_IRQn = 37, /*!< PL011 Interrupt */
: :
: :
} IRQn_Type;
\endcode
\section core_config_sect Configuration of the Processor and Core Peripherals
The \ref device_h_pg configures the Cortex-A processor and the core peripherals with <i>\#defines</i>
that are set prior to including the file <b>core_<cpu>.h</b>.
The following tables list the <i>\#defines</i> along with the possible values for each processor core.
If these <i>\#defines</i> are missing default values are used.
<table class="cmtable">
<tr>
<th>\#define</th>
<th>Value Range</th>
<th>Default</th>
<th>Description</th>
</tr>
<tr>
<td>__CM0_REV</td>
<td>0x0000</td>
<td>0x0000</td>
<td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
</tr>
<tr>
<td>__CORTEX_A</td>
<td>5, 7, 9</td>
<td>(n/a)</td>
<td>Core type number</td>
</tr>
<tr>
<td>__FPU_PRESENT</td>
<td>0 .. 1</td>
<td>0</td>
<td>Defines if an FPU is present or not</td>
</tr>
<tr>
<td>__GIC_PRESENT</td>
<td>0 ..1 </td>
<td>Defines if an GIC is present or not</td>
<td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
</tr>
<tr>
<td>__TIM_PRESENT</td>
<td>0 .. 1</td>
<td>0</td>
<td>Defines if a private timer is present or not</td>
</tr>
<tr>
<td>__L2C_PRESENT</td>
<td>0 .. 1</td>
<td>0</td>
<td>Defines if a level 2 cache controller is present or not</td>
</tr>
</table>
\b Example
The following code exemplifies the configuration of the Cortex-A9 Processor and Core Peripherals.
\code
#define __CA_REV 0x0000U /*!< Core revision r0p0 */
#define __CORTEX_A 9U /*!< Cortex-A9 Core */
#define __FPU_PRESENT 1U /*!< FPU present */
#define __GIC_PRESENT 1U /*!< GIC present */
#define __TIM_PRESENT 0U /*!< TIM not present */
#define __L2C_PRESENT 0U /*!< L2C not present */
:
:
#include "core_ca.h" /* Cortex-A processor and core peripherals */
\endcode
\section core_version_sect CMSIS Version and Processor Information
Defines in the core_<i>cpu</i>.h file identify the version of the CMSIS-Core-A and the processor used.
The following shows the defines in the various core_<i>cpu</i>.h files that may be used in the \ref device_h_pg
to verify a minimum version or ensure that the right processor core is used.
\code
#define __CA_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS Core main version */
#define __CA_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS Core sub version */
#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
__CA_CMSIS_VERSION_SUB ) /* CMSIS Core version number */
\endcode
\section device_access Device Peripheral Access Layer
The \ref device_h_pg contains for each peripheral:
- Register Layout Typedef
- Base Address
- Access Definitions
The section \ref peripheral_gr shows examples for peripheral definitions.
\section device_h_sec Device.h Template File
The silicon vendor needs to extend the Device.h template file with the CMSIS features described above.
In addition the \ref device_h_pg may contain functions to access device-specific peripherals.
The \ref system_Device_h_sec which is provided as part of the CMSIS specification is shown below.
\verbinclude "Include/Device.h"
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\page mem_h_pg Memory Configuration Files mem_<device>.h
\verbinclude "Include/mem_Device.h"
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\page mmu_c_pg Memory Management Unit Files mmu_<device>.c
\verbinclude "Source/mmu_Device.c"
*/

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/**
\page using_pg Using CMSIS in Embedded Applications
\details
To use the CMSIS-Core-A the following files are added to the embedded application:
- \ref startup_c_pg with reset handler and exception vectors.
- \ref system_c_pg with general device configuration (i.e. for clock and bus setup).
- \ref device_h_pg gives access to processor core and all peripherals.
- \ref mem_h_pg contains basic memory configurations.
- \ref mmu_c_pg contains the memory management unit setup.
\note The files \ref startup_c_pg, \ref system_c_pg, \ref mem_h_pg, and \ref mmu_c_pg may require application specific adaptations and therefore should be copied
into the application project folder prior configuration. The \ref device_h_pg is included in all source files that need device access
and can be stored on a central include folder that is generic for all projects.
The \ref Reset_Handler defined in \ref startup_c_pg is executed after reset.
The default initialization sequence is
- set the vector base address register (\ref __set_VBAR),
- set stacks for each exception mode (\ref __set_mode, \ref __set_SP),
- call \ref SystemInit.
After the system initialization control is transferred to the C/C++ run-time
library which performs initialization and calls the \b main function in the user code. In addition the \ref startup_c_pg contains a weak default handler
implementation for every exception. It may also contain stack and heap configurations for the user application.
The \ref system_c_pg performs the setup for the processor clock and the initialization of memory caches, memory management unit, generic interrupt interface
and floating point unit. The variable \ref SystemCoreClock indicates the CPU clock speed.
\ref system_init_gr describes the minimum feature set. In addition the file may contain functions for the memory bus setup and clock re-configuration.
The \ref device_h_pg is the central include file that the application programmer is using in the C/C++ source code. It provides the following features:
- \ref peripheral_gr provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.
- \ref GIC_functions can be accessed with standardized symbols and functions for the General Interrupt Controller (GIC) are provided.
- \ref CMSIS_Core_InstructionInterface allow to access special instructions, for example for activating sleep mode or the NOP instruction.
- \ref PL1_timer_functions "Generic" and \ref PTM_timer_functions "Private" Timer functions to configure and start a periodic timer interrupt.
- \ref L1_cache_functions "Level 1" and \ref L2_cache_functions "Level 2" Cache controller functions to enable, disable, clean and invalidate caches.
CMSIS-Pack provides the <b>\#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to this <b><i>device</i>.h</b> file.
\image html "CMSIS_CORE_A_Files_user.png" "CMSIS-Core-A User Files"
The CMSIS-Core-A user files are device specific. In addition, the \ref startup_c_pg is also compiler vendor specific.
The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.
\note The silicon vendors create these device-specific CMSIS-Core-A files based on \ref templates_pg provide by Arm.
Thereafter, the functions described under <a href="modules.html">\b Reference </a> can be used in the application.
\b Examples
- \subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.
- \subpage using_ARM_pg explains how to use CMSIS-Core-M for Arm processors.
\page using_CMSIS Basic CMSIS Example
A typical example for using the CMSIS layer is provided below. The example is based on an unspecific Cortex-A9 Device.
\code
#include <ARMCA9.h> // File name depends on device used
static const uint32_t TICK_RATE_HZ = 1000U;
uint32_t volatile msTicks; // Counter for millisecond Interval
static void SysTick_Handler( void )
{
msTicks++; // Increment Counter
}
// We use the Private Tiemer (PTIM) of the Cortex-A9 FVP Model here.
// In general the available Timers are highly vendor specific for Cortex-A processors.
void private_timer_init(void) {
PTIM_SetLoadValue ((SystemCoreClock/TICK_RATE_HZ) - 1U);
PTIM_SetControl (PTIM_GetControl() | 7U);
/* Install SysTick_Handler as the interrupt function for PTIM */
IRQ_SetHandler((IRQn_ID_t)PrivTimer_IRQn, SysTick_Handler);
/* Determine number of implemented priority bits */
IRQ_SetPriority ((IRQn_ID_t)PrivTimer_IRQn, IRQ_PRIORITY_Msk);
/* Set lowest priority -1 */
IRQ_SetPriority ((IRQn_ID_t)PrivTimer_IRQn, GIC_GetPriority((IRQn_ID_t)PrivTimer_IRQn)-1);
/* Enable IRQ */
IRQ_Enable ((IRQn_ID_t)PrivTimer_IRQn);
}
/* Delay execution for given amount of ticks */
void Delay(uint32_t ticks) {
uint32_t tgtTicks = msTicks + ticks; // target tick count to delay execution to
while (msTicks == tgtTicks) {
__WFE (); // Power-Down until next Event/Interrupt
}
}
/* main function */
int main(void)
{
/* Initialize device HAL here */
private_timer_init();
static uint8_t ledState = 0;
/* Infinite loop */
while (1)
{
/* Add application code here */
ledState = !ledState;
Delay(500);
}
}
\endcode
CMSIS-Pack provides the <b>\#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file
of a project. This allows you to generate generic software components that use the device selected in a project.
\code
#include "RTE_Components.h" // include information about project configuration
#include CMSIS_device_header // include <device>.h file
\endcode
\page using_ARM_pg Using CMSIS with generic Arm Processors
Arm provides CMSIS-Core-A files for the supported Arm Processors and for various compiler vendors.
These files can be used when standard Arm processors should be used in a project.
The table below lists the folder and device names of the Arm processors.
<table class="cmtable">
<tr>
<th>Folder</th>
<th>Processor</th>
<th>Description</th>
</tr>
<tr>
<td>".\Device\ARM\ARMCA5"</td>
<td>Cortex-A5</td>
<td>Contains \b Include and \b Source template files configured for the Cortex-A5 processor.
The device name is ARMCA5 and the name of the \ref device_h_pg is <ARMCA5.h>.
</td>
</tr>
<tr>
<td>".\Device\ARM\ARMCA7"</td>
<td>Cortex-A7</td>
<td>Contains \b Include and \b Source template files configured for the Cortex-A7 processor.
The device name is ARMCA7 and the name of the \ref device_h_pg is <ARMCA7.h>.
</td>
</tr>
<tr>
<td>".\Device\ARM\ARMCA9"</td>
<td>Cortex-A9</td>
<td>Contains \b Include and \b Source template files configured for the Cortex-A9 processor.
The device name is ARMCA9 and the name of the \ref device_h_pg is <ARMCA9.h>.
</td>
</tr>
</table>
\note
CMSIS-Pack provides the <b>\#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file
of a project. This allows you to generate generic software components that adjust to the device settings.
*/

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/**************************************************************************//**
* @file cmsis_armcc.txt
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.00
* @date 22. Feb 2017
******************************************************************************/
/* CMSIS compiler control architecture macros */
/**
\defgroup comp_cntrl_gr Compiler Control
\brief Compiler agnostic \#define symbols for generic C/C++ source code
\details
The CMSIS-Core provides the header file \b cmsis_compiler.h with consistent \#define symbols to generate C or C++ source files that should be compiler agnostic.
Each CMSIS compliant compiler should support the functionality described in this section.
@{
*/
/**
\def __ARMCC_VERSION
*/
/**
\def __ARM_ARCH_7A__
\brief Set to 1 when generating code for Armv7-A (Cortex-A7)
\details
The \b \#define __ARM_ARCH_7A__ is set to 1 when generating code for the Armv7-A architecture. This architecture is for example used by the Cortex-A7 processor.
*/
/**
\def __ASM
\brief Pass information from the compiler to the assembler.
\details
The \b __ASM keyword can declare or define an embedded assembly function or incorporate inline assembly into a function
(shown in the code example below).
<b>Code Example:</b>
\code
// Reverse bit order of value
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
\endcode
*/
/**
\def __INLINE
\brief Recommend that function should be inlined by the compiler.
\details
Inline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to
inline code or not. The \b __INLINE attribute gives the compiler an hint to inline this function.
Still, the compiler may decide not to inline the function. As the function is global an callable function is also generated.
<b> Code Example:</b>
\code
const uint32_t led_mask[] = {1U << 4, 1U << 5, 1U << 6, 1U << 7};
//------------------------------------------------------------------------------
// Switch on LEDs
//------------------------------------------------------------------------------
__INLINE static void LED_On (uint32_t led) {
PTD->PCOR = led_mask[led];
}
\endcode
*/
/**
\def __STATIC_INLINE
\brief Define a static function should be inlined by the compiler.
\details
Defines a static function that may be inlined by the compiler. If the compiler generates inline code for
all calls to this functions, no additional function implementation is generated which may further optimize space.
<b> Code Example:</b>
\code
__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
{
return((uint32_t)GICDistributor->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)]);
}
\endcode
*/
/**************************************************************************************************/
/**
\def __STATIC_FORCEINLINE
\brief Define a static function that should be always inlined by the compiler.
\details
Defines a static function that should be always inlined by the compiler.
\note
For compilers that do not allow to force function inlining, the macro maps to \ref __STATIC_INLINE.
<b> Code Example:</b>
\code
\\ Get Interrupt Vector
__STATIC_FORCEINLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
\endcode
*/
#define __STATIC_FORCEINLINE
/**
\def __NO_RETURN
\brief Inform the compiler that a function does not return.
\details
Informs the compiler that the function does not return. The compiler can then perform optimizations by
removing code that is never reached.
<b> Code Example:</b>
\code
// OS idle demon (running when no other thread is ready to run).
__NO_RETURN void os_idle_demon (void);
\endcode
*/
/**
\def __USED
\brief Inform that a variable shall be retained in executable image.
\details
Definitions tagged with \b __USED in the source code should be not removed by the linker when detected as unused.
<b> Code Example:</b>
\code
// Export following variables for debugging
__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
__USED uint32_t const os_clockrate = OS_TICK;
__USED uint32_t const os_timernum = 0;
\endcode
**/
/**
\def __WEAK
\brief Export a function or variable weakly to allow overwrites.
\details
Functions defined with \b __WEAK export their symbols weakly. A function defined weak behaves like a normal defined
function unless a non-weak function with the same name is linked into the same image. If both a non-weak
function and a weak defined function exist in the same image, then all calls to the function resolve to the non-weak
function.
Functions declared with \b __WEAK and then defined without \b __WEAK behave as non-weak functions.
<b> Code Example:</b>
\code
__WEAK void SystemInit(void)
{
SystemCoreSetup();
SystemCoreClockSetup();
}
\endcode
*/
/**
\def __ALIGNED(x)
\brief Minimum alignment for a variable.
\details
Specifies a minimum alignment for a variable or structure field, measured in bytes.
<b> Code Example:</b>
\code
uint32_t stack_space[0x100] __ALIGNED(8); // 8-byte alignment required
\endcode
*/
/**
\def __PACKED
\brief Request smallest possible alignment.
\details
Specifies that a type must have the smallest possible alignment.
<b> Code Example:</b>
\code
struct foo {
uint8_t u8;
uint32_t u32[2] __PACKED;
};
\endcode
*/
/**************************************************************************************************/
/**
\def __PACKED_STRUCT
\brief Request smallest possible alignment for a structure.
\details
Specifies that a structure must have the smallest possible alignment.
<b> Code Example:</b>
\code
__PACKED_STRUCT foo {
uint8_t u8;
uint32_t u32;
uint16_t u16;
};
\endcode
*/
#define __PACKED_STRUCT
/**************************************************************************************************/
/**
\def __UNALIGNED_UINT32
\brief Pointer for unaligned access of a uint32_t variable.
\deprecated
Do not use this macro.
It has been superseded by \ref __UNALIGNED_UINT32_READ, \ref __UNALIGNED_UINT32_WRITE and will be removed in the future.
\details
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
\code
uint32_t val32;
void test (uint8_t *ptr) {
__UNALIGNED_UINT32(ptr) = val32;
}
\endcode
*/
#define __UNALIGNED_UINT32
/**************************************************************************************************/
/**
\def __UNALIGNED_UINT16_READ
\brief Pointer for unaligned read of a uint16_t variable.
\details
Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
\code
uint16_t val16;
void test (uint8_t *ptr) {
val16 = __UNALIGNED_UINT16_READ(ptr);
}
\endcode
*/
#define __UNALIGNED_UINT16_READ
/**************************************************************************************************/
/**
\def __UNALIGNED_UINT16_WRITE
\brief Pointer for unaligned write of a uint16_t variable.
\details
Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
\code
uint16_t val16 = 0U;
void test (uint8_t *ptr) {
__UNALIGNED_UINT16_WRITE(ptr, val16);
}
\endcode
*/
#define __UNALIGNED_UINT16_WRITE
/**************************************************************************************************/
/**
\def __UNALIGNED_UINT32_READ
\brief Pointer for unaligned read of a uint32_t variable.
\details
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
\code
uint32_t val32;
void test (uint8_t *ptr) {
val32 = __UNALIGNED_UINT32_READ(ptr);
}
\endcode
*/
#define __UNALIGNED_UINT32_READ
/**************************************************************************************************/
/**
\def __UNALIGNED_UINT32_WRITE
\brief Pointer for unaligned write of a uint32_t variable.
\details
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
processor core and compiler settings.
<b> Code Example:</b>
\code
uint32_t val32 = 0U;
void test (uint8_t *ptr) {
__UNALIGNED_UINT32_WRITE(ptr, val32);
}
\endcode
*/
#define __UNALIGNED_UINT32_WRITE
/**
@}
*/
/* end group comp_cntrl_gr */
/* ########################## Core Instruction Access ######################### */
/**
\defgroup CMSIS_Core_InstructionInterface Intrinsic Functions
\brief Functions that generate specific Cortex-A CPU Instructions
@{
*/
/**
\def __NOP
\details No Operation does nothing. This instruction can be used for code alignment purposes.
\def __WFI
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
\def __WFE
\details Wait For Event is a hint instruction that permits the processor to enter
\def __SEV
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
\def __ISB()
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
\def __DSB()
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
\def __DMB()
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
\def __BKPT(value)
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
*/
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
uint32_t __REV(uint32_t value);
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
uint16_t __REV16(uint16_t value);
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
int32_t __REVSH(int32_t value);
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
uint32_t __ROR(uint32_t op1, uint32_t op2);
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
uint32_t __RBIT(uint32_t value);
/**
\brief Count leading zeros.
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
uint8_t __CLZ(uint32_t value);
/** @}*/
/* end of group CMSIS_Core_InstructionInterface */

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/**************************************************************************//**
* @file cmsis_compiler.txt
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.00
* @date 22. Feb 2017
******************************************************************************/

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/**************************************************************************//**
* @file core_ca.txt
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
******************************************************************************/
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup peripheral_gr Peripheral Access
\brief Naming conventions and optional features for accessing peripherals.
\details
The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals.
Most of the rules also apply to the core peripherals. The \ref device_h_pg "Device Header File \<device.h>" contains typically these definition and also includes
the core specific header files.
The definitions for \ref peripheral_gr can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals.
Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.
Each peripheral provides a data type definition with a name that is composed of:
- an optional prefix <b>&lt;<i>device abbreviation&gt;</i>_</b>
- <b>&lt;<i>peripheral name</i>&gt;</b>
- postfix \b _Type or \b _TypeDef to identify a type definition.
Examples:
- \b UART_TypeDef for the peripheral \b UART.
- \b IMX_UART_TypeDef for the device family \b IMX and the peripheral \b UART.
The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.
- IO Type Qualifiers are used to specify the access to peripheral variables.
IO Type Qualifier | Type | Description
:------------------|:----------------|:------------
\b __IM | Struct member | Defines 'read only' permissions
\b __OM | Struct member | Defines 'write only' permissions
\b __IOM | Struct member | Defines 'read / write' permissions
\b __I | Scalar variable | Defines 'read only' permissions
\b __O | Scalar variable | Defines 'write only' permissions
\b __IO | Scalar variable | Defines 'read / write' permissions
The typedef <b>\<<i>device abbreviation</i>\>_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.
\code
typedef struct {
__O uint32_t UART_CR; // Offset: 0x0000 ( /W) Control Register
__IO uint32_t UART_MR; // Offset: 0x0004 (R/W) Mode Register
__O uint32_t UART_IER; // Offset: 0x0008 ( /W) Interrupt Enable Register
__O uint32_t UART_IDR; // Offset: 0x000C ( /W) Interrupt Disable Register
__I uint32_t UART_IMR; // Offset: 0x0010 (R/ ) Interrupt Mask Register
__I uint32_t UART_SR; // Offset: 0x0014 (R/ ) Status Register
__I uint32_t UART_RHR; // Offset: 0x0018 (R/ ) Receive Holding Register
__O uint32_t UART_THR; // Offset: 0x001C ( /W) Transmit Holding Register
__IO uint32_t UART_BRGR; // Offset: 0x0020 (R/W) Baud Rate Generator Register
__IO uint32_t UART_CMPR; // Offset: 0x0024 (R/W) Comparison Register
__IO uint32_t UART_RTOR; // Offset: 0x0028 (R/W) Receiver Time-out Register
__I uint32_t RESERVED[46]; // Offset: 0x002C (R/ ) Reserved
__IO uint32_t UART_WPMR; // Offset: 0x00E4 (R/W) Write Protection Mode Register
} IMX_UART_TypeDef;
\endcode
To access the registers of the UART defined above, pointers to this register structure are defined.
If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.
\b Example:
In this example, \b IMX_UART2 and \b IMX_UART3 are two pointers to UARTs defined with above register structure.
\n
\code
#define IMX_UART2 ((IMX_UART_TypeDef *) IMX_UART2_BASE)
#define IMX_UART3 ((IMX_UART_TypeDef *) IMX_UART3_BASE)
\endcode
\note
- The prefix <b>IMX</b> is optional.
The registers in the various UARTs can now be referred in the user code as shown below:\n
\code
val = IMX_UART2->SR // is the Status Register of UART2.
\endcode
<hr>
\section core_cmsis_pal_min_reqs Minimal Requirements
\details
To access the peripheral registers and related function in a device, the files <b><i>device.h</i></b> and <b>core_ca.h</b> define as a minimum:
\n\n
- The <b>Register Layout Typedef</b> for each peripheral that defines all register names.
RESERVED is used to introduce space into the structure for adjusting the addresses of
the peripheral registers.
\n\n
<b>Example:</b>
\code
typedef struct
{
__IOM uint32_t C_CTLR; // Offset: 0x0000 (R/W) CPU Interface Control Register
__IOM uint32_t C_PMR; // Offset: 0x0004 (R/W) Interrupt Priority Mask Register
__IOM uint32_t C_BPR; // Offset: 0x0008 (R/W) Binary Point Register
__IM uint32_t C_IAR; // Offset: 0x000C (R/ ) Interrupt Acknowledge Register
__OM uint32_t C_EOIR; // Offset: 0x0010 ( /W) End Of Interrupt Register
__IM uint32_t C_RPR; // Offset: 0x0014 (R/ ) Running Priority Register
__IM uint32_t C_HPPIR; // Offset: 0x0018 (R/ ) Highest Priority Pending Interrupt Register
__IOM uint32_t C_ABPR; // Offset: 0x001C (R/W) Aliased Binary Point Register
__IM uint32_t C_AIAR; // Offset: 0x0020 (R/ ) Aliased Interrupt Acknowledge Register
__OM uint32_t C_AEOIR; // Offset: 0x0024 ( /W) Aliased End Of Interrupt Register
__IM uint32_t C_AHPPIR; // Offset: 0x0028 (R/ ) Aliased Highest Priority Pending Interrupt Register
__IOM uint32_t C_STATUSR; // Offset: 0x002C (R/W) Error Reporting Status Register, optional
__I uint32_t RESERVED1[40]; // Offset: 0x0030 (R/ ) Reserved
__IOM uint32_t C_APR[4]; // Offset: 0x00D0 (R/W) Active Priority Register
__IOM uint32_t C_NSAPR[4]; // Offset: 0x00E0 (R/W) Non-secure Active Priority Register
__I uint32_t RESERVED2[3]; // Offset: 0x00F6 (R/ ) Reserved
__IM uint32_t C_IIDR; // Offset: 0x00FC (R/ ) CPU Interface Identification Register
__I uint32_t RESERVED3[960]; // Offset: 0x0100 (R/ ) Reserved
__OM uint32_t C_DIR; // Offset: 0x1000 ( /W) Deactivate Interrupt Register
} GICInterface_Type;
\endcode
- <b>Base Address</b> for each peripheral (in case of multiple peripherals
that use the same <b>register layout typedef</b> multiple base addresses are defined).
\n\n
<b>Example:</b>
\code
#define GIC_INTERFACE_BASE (0xe8202000UL) // GIC Interface Base Address
\endcode
- <b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same
<b>register layout typedef</b>, multiple access definitions exist.
\n\n
<b>Example:</b>
\code
#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE) // GIC Interface Access Definition
\endcode
These definitions allow accessing peripheral registers with simple assignments.
- <b>Example:</b>
\n
\code
GICInterface->C_CTLR |= 1; // Enable Interface
\endcode
<hr>
\section core_cmsis_pal_opts Optional Features
\details
Optionally, the file <b><i>device</i>.h</b> may define:
- \ref core_cmsis_pal_bitfields and \#define constants that simplify access to peripheral registers.
These constants may define bit-positions or other specific patterns that are required for
programming peripheral registers. The identifiers should start with
<b>&lt;<i>device abbreviation</i>&gt;_</b> and <b>&lt;<i>peripheral name</i>&gt;_</b>.
It is recommended to use CAPITAL letters for \#define constants.
- More complex functions (i.e. status query before
a sending register is accessed). Again, these functions start with
<b>&lt;<i>device abbreviation</i>&gt;_</b> and <b>&lt;<i>peripheral name</i>&gt;_</b>.
<hr>
\section core_cmsis_pal_bitfields Register Bit Fields
\details
For Core Register, macros define the position and the mask value for a bit field.
<b>Example:</b>
Bit field definitions for register ACTLR in CP15.
\code
// CP15 Register ACTLR
#define ACTLR_DDI_Pos 28U
#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos)
#define ACTLR_DDVM_Pos 15U
#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos)
#define ACTLR_L1PCTL_Pos 13U
#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos)
#define ACTLR_L1RADIS_Pos 12U
#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos)
#define ACTLR_L2RADIS_Pos 11U
#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos)
#define ACTLR_DODMBS_Pos 10U
#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos)
#define ACTLR_SMP_Pos 6U
#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos)
\endcode
The macros <b>_VAL2FLD(field, value)</b> and <b>_FLD2VAL(field, value)</b> enable access to bit fields.
@{
*/
/**
\def _VAL2FLD(field, value)
\param field name of bit field.
\param value value for the bit field. This parameter is interpreted as an uint32_t type.
\brief Mask and shift a bit field value for assigning the result to a peripheral register.
\details
The macro \ref _VAL2FLD uses the \#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to shift bit-field values for
assigning to a register.
<b>Example:</b>
\code
ACTLR = _VAL2FLD(ACTLR_SMP, 0x1)
\endcode
*/
#define _VAL2FLD(field, value)
/**
\def _FLD2VAL(field, value)
\param field name of bit field.
\param value value of the register. This parameter is interpreted as an uint32_t type.
\brief Extract from a peripheral register value the a bit field value.
\details
The macro \ref _FLD2VAL uses the \#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to extract the value of a bit field from a register.
<b>Example:</b>
\code
i = _FLD2VAL(ACTLR_SMP, ACTLR);
\endcode
*/
#define _FLD2VAL(field, value)
/** @} */
/*end of group peripheral_gr */
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\defgroup version_ctrl Version Control
\brief Version symbols for CMSIS release specific C/C++ source code.
@{
*/
/* CMSIS CA definitions */
/**
\def __CA_CMSIS_VERSION_MAIN
\details
Use this define to query the major version of CMSIS-Core(A) component.
\b Example:
\code
#if __CA_CMSIS_VERSION_MAIN < 5
#error This code needs at least CMSIS-Core(A) version 5!
#endif
\endcode
\def __CA_CMSIS_VERSION_SUB
\details
Use this define to query the minor version of CMSIS-Core(A) component.
\b Example:
\code
#if __CA_CMSIS_VERSION_MAIN < 5
#error This code needs at least CMSIS-Core(A) version 5!
#else
#if __CA_CMSIS_VERSION_SUB < 1
#warning Using CMSIS-Core(A) version 5.0 compatibility functions.
#endif
#endif
\endcode
\def __CA_CMSIS_VERSION
\details
Use this define to query the full version of CMSIS-Core(A) component.
| Bits | Name | Function |
| :------ | :------------ | :-----------------------|
| [31:16] | MAIN | __CA_CMSIS_VERSION_MAIN |
| [15:0] | SUB | __CA_CMSIS_VERSION_SUB |
\b Example:
\code
#if __CA_CMSIS_VERSION < 0x00050001
#error This code needs at least CMSIS-Core(A) version 5.1!
#endif
\endcode
\def __CA_REV
\brief Contains the core revision for a Cortex-A class device.
\details
Use this define to query the core design revision number implemented in the selected device.
| Bits | Name | Function |
| :------ | :------------ | :---------------|
| [15:8] | REV | Revision number |
| [7:0] | PATCH | Patch number |
\b Example:
\code
#if __CA_REV < 0x0201
#error This code needs at least a core revision r2p1.
#endif
\endcode
\def __CORTEX_A
\brief Contains the core family for a Cortex-A class device.
\details
Use this define to query the actual Cortex-A class device number implemented in the selected device.
\b Example:
\code
#if __CORTEX_A == 5
#warning Running on Cortex-A5.
#elif __CORTEX_A == 7
#warning Running on Cortex-A7.
#elif __CORTEX_A == 9
#warning Running on Cortex-A9.
#endif
\endcode
*/
/** @} */
/*end of group version_ctrl */
/**
\defgroup CMSIS_Core_FunctionInterface Core Peripherals
\brief
\details
Hardware Abstraction Layer.
The Core-A function interface contains:
- \ref FPU_functions
- \ref GIC_functions
- \ref L1_cache_functions
- \ref L2_cache_functions
- \ref MMU_functions
- \ref PL1_timer_functions
- \ref PTM_timer_functions
*/
/* ########################## FPU functions ############################ */
/**
\defgroup FPU_functions Floating Point Unit Functions
\ingroup CMSIS_Core_FunctionInterface
\brief FPU Functions enable the use of Floating Point instructions and extensions.\n
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.
@{
\fn __STATIC_INLINE __ASM void __FPU_Enable(void)
@}
*/

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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
// ==== IRQ Controller API ====
/**
\defgroup irq_ctrl_gr Interrupts and Exceptions
\brief Generic functions to access the Interrupt Controller.
\details This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers.
The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.
\note The default implementation for \ref GIC_functions "Arm GIC (Generic Interrupt Controller)" can be found in \ref irq_ctrl_gic.c.
It uses \c weak functions thus it can easily be overwritten by an alternative user implementation if needed.
The Armv7-A architecture defines a common set of first level exceptions, see table below.
| Exception | CMSIS Handler | Offset | Description |
|-------------------------------|---------------|--------|-----------------------------------------------------------------------------|
| Reset | Reset_Handler | 0x0000 | First instruction executed after reset. |
| Undefined Instruction (Undef) | Undef_Handler | 0x0004 | Signals usage of an illegal instructions. |
| Supervisor Call (SVC) | SVC_Handler | 0x0008 | Issued by software using SVC instruction. |
| Prefetch Abort (PAbt) | PAbt_Handler | 0x000C | Signals a memory abort on istruction fetch. |
| Data Abort (DAbt) | DAbt_Handler | 0x0010 | Signals a memory abort on data read or write. |
| Hyp Trap | (NOP) | 0x0014 | Hypervisor instruction trap, only available with Virtualization Extensions. |
| IRQ interrupt | IRQ_Handler | 0x0018 | Interrupt Request (typically from Interrupt Controller) |
| FIQ interrupt | FIQ_Handler | 0x001C | Fast Interrupt Request (typically from Interrupt Controller) |
By default those handlers are defined as weak empty functions by the \ref startup_c_sec "device specific startup code".
Software and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to
be implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using
<a href="../../RTOS2/html/rtx5_impl.html">RTX5</a>.
The interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined
as \ref IRQn_Type in \ref device_h_pg. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes
and preemption rules, and register interrupt callbacks.
\b Example:
\code
void SGI0_Handler() {
/*
* Handle Interrupt
*/
IRQ_ClearPending((IRQn_ID_t)SGI0_IRQn);
}
void main() {
/* Initialize the Interrupt Controller */
IRQ_Initialize();
/* Register the user defined handler function */
IRQ_SetHandler((IRQn_ID_t)SGI0_IRQn, SGI0_Handler);
/* Set the priority considering the priority grouping */
const uint32_t subprio = IRQ_GetPriorityGroupBits();
IRQ_SetPriority((IRQn_ID_t)SGI0_IRQn, 1u << subprio);
/* Set interrupt mode to falling edge */
IRQ_SetMode((IRQn_ID_t)SGI0_IRQn, IRQ_MODE_TYPE_IRQ | IRQ_MODE_CPU_0 | IRQ_MODE_TRIG_EDGE | IRQ_MODE_TRIG_EDGE_FALLING);
IRQ_Enable((IRQn_ID_t)SGI0_IRQn);
/* Trigger interrupt */
IRQ_SetPending((IRQn_ID_t)SGI0_IRQn);
IRQ_Disable((IRQn_ID_t)SGI0_IRQn);
}
\endcode
@{
*/
/**
\defgroup irq_mode_defs IRQ Mode Bit-Masks
\brief Configure interrupt line mode
\details
@{
The following codes are used as values for the parameter \em mode of the function \ref IRQ_SetMode to configure interrupt line mode.
They are also returned by the function \ref IRQ_GetMode when retrieving interrupt line mode.
The values of \b IRQ_MODE_TRIG_x definitions specify
The values of \b IRQ_MODE_TYPE_x definitions specify
The values of \b IRQ_MODE_DOMAIN_x definitions specify
The values of \b IRQ_MODE_CPU_x definitions specify
// Interrupt mode bit-masks
\def IRQ_MODE_TRIG_LEVEL
\def IRQ_MODE_TRIG_LEVEL_LOW
\def IRQ_MODE_TRIG_LEVEL_HIGH
\def IRQ_MODE_TRIG_EDGE
\def IRQ_MODE_TRIG_EDGE_RISING
\def IRQ_MODE_TRIG_EDGE_FALLING
\def IRQ_MODE_TRIG_EDGE_BOTH
\def IRQ_MODE_TYPE_IRQ
\def IRQ_MODE_TYPE_FIQ
\def IRQ_MODE_DOMAIN_NONSECURE
\def IRQ_MODE_DOMAIN_SECURE
\def IRQ_MODE_CPU_ALL
\def IRQ_MODE_CPU_0
\def IRQ_MODE_CPU_1
\def IRQ_MODE_CPU_2
\def IRQ_MODE_CPU_3
\def IRQ_MODE_CPU_4
\def IRQ_MODE_CPU_5
\def IRQ_MODE_CPU_6
\def IRQ_MODE_CPU_7
\def IRQ_MODE_ERROR
@}
*/
/**
\defgroup irq_priority_defs IRQ Priority Bit-Masks
\brief Definitions used by interrupt priority functions.
\details
@{
The following values are used by the interrupt priority functions.
The value of \b IRQ_PRIORITY_Msk specifies maximum interrupt priority value and can be used as parameter for the functions
\ref IRQ_GetPriority and \ref IRQ_SetPriorityGroupBits to retrieve implementation specific priority values.
The value of \b IRQ_PRIORITY_ERROR is used by functions \ref IRQ_GetPriority, IRQ_GetPriorityMask and \ref IRQ_GetPriorityGroupBits
to signal function execution error.
\def IRQ_PRIORITY_Msk
\def IRQ_PRIORITY_ERROR
@}
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_Initialize (void)
\details This function initializes interrupt controller.
It disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and
configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should
be set to NULL.
For Arm GIC the default implementation looks like the following example:
\code
/// Number of implemented interrupt lines
#ifndef IRQ_GIC_LINE_COUNT
#define IRQ_GIC_LINE_COUNT (1020U)
#endif
static IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
int32_t IRQ_Initialize (void) {
uint32_t i;
for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
IRQTable[i] = (IRQHandler)NULL;
}
GIC_Enable();
return (0);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler)
\details This function registers address of the interrupt handler callback function corresponding to the specified interrupt
ID number.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
IRQTable[irqn] = handler;
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn)
\details This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt
ID number.
For Arm GIC the default implementation looks like the following example:
\code
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
IRQHandler h;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
h = IRQTable[irqn];
} else {
h = (IRQHandler_t)0;
}
return (h);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_Enable (IRQn_ID_t irqn)
\details This function enables forwarding of the corresponding interrupt to the CPU.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_Enable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_EnableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_Disable (IRQn_ID_t irqn)
\details This function disables forwarding of the corresponding interrupt to the CPU.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_Disable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_DisableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn uint32_t IRQ_GetEnableState (IRQn_ID_t irqn)
\details This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter.
Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts
which cannot be identified by irqn.
For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
uint32_t enable;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
} else {
enable = 0U;
}
return (enable);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode)
\details This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt
(see \ref irq_mode_defs) identified by the irqn parameter.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
int32_t status;
uint32_t val;
uint8_t cfg;
uint8_t secure;
uint8_t cpu;
status = 0;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
// Check triggering mode
val = (mode & IRQ_MODE_TRIG_Msk);
if (val == IRQ_MODE_TRIG_LEVEL) {
cfg = 0x00U;
} else if (val == IRQ_MODE_TRIG_EDGE) {
cfg = 0x02U;
} else {
status = -1;
}
// Check interrupt type
val = mode & IRQ_MODE_TYPE_Msk;
if (val != IRQ_MODE_TYPE_IRQ) {
status = -1;
}
// Check interrupt domain
val = mode & IRQ_MODE_DOMAIN_Msk;
if (val == IRQ_MODE_DOMAIN_NONSECURE) {
secure = 0;
} else {
// Check security extensions support
val = GIC_DistributorInfo() & (1UL << 10U);
if (val != 0U) {
// Security extensions are supported
secure = 1;
} else {
status = -1;
}
}
// Check interrupt CPU targets
val = mode & IRQ_MODE_CPU_Msk;
if (val == IRQ_MODE_CPU_ALL) {
cpu = 0xFF;
} else {
cpu = val >> IRQ_MODE_CPU_Pos;
}
// Apply configuration if no mode error
if (status == 0) {
GIC_SetConfiguration((IRQn_Type)irqn, cfg);
GIC_SetTarget ((IRQn_Type)irqn, cpu);
if (secure != 0U) {
GIC_SetGroup ((IRQn_Type)irqn, secure);
}
}
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn uint32_t IRQ_GetMode (IRQn_ID_t irqn)
\details This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter.
\ref IRQ_MODE_ERROR is returned for interrupts which cannot be identified by irqn.
For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
uint32_t mode;
uint32_t val;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
mode = IRQ_MODE_TYPE_IRQ;
// Get trigger mode
val = GIC_GetConfiguration((IRQn_Type)irqn);
if ((val & 2U) != 0U) {
// Corresponding interrupt is edge triggered
mode |= IRQ_MODE_TRIG_EDGE;
} else {
// Corresponding interrupt is level triggered
mode |= IRQ_MODE_TRIG_LEVEL;
}
// Get interrupt CPU targets
mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
} else {
mode = IRQ_MODE_ERROR;
}
return (mode);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn IRQn_ID_t IRQ_GetActiveIRQ (void)
\details This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt.
For Arm GIC the default implementation looks like the following example:
\code
IRQn_ID_t IRQ_GetActiveIRQ (void) {
IRQn_ID_t irqn;
irqn = (IRQn_ID_t)GIC_AcknowledgePending();
return (irqn);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn IRQn_ID_t IRQ_GetActiveFIQ (void)
\details This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.
For Arm GIC the default implementation looks like the following example:
\code
IRQn_ID_t IRQ_GetActiveFIQ (void) {
// FIQ is not supported, return invalid ID
return ((IRQn_ID_t)-1);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn)
\details This function informs the interrupt controller that the interrupt service routine processing of the currently
active interrupt request is completed.
The parameter irqn should specify the value previously returned by the \ref IRQ_GetActiveIRQ or \ref IRQ_GetActiveFIQ functions.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_EndInterrupt ((IRQn_Type)irqn);
if (irqn == 0) {
IRQ_ID0 = 0U;
}
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_SetPending (IRQn_ID_t irqn)
\details This function sets the pending status of the interrupt identified by the irqn parameter.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_SetPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn uint32_t IRQ_GetPending (IRQn_ID_t irqn)
\details This function retrieves the pending status of the interrupt identified by the irqn parameter.
Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which
cannot be identified by irqn.
For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
uint32_t pending;
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
} else {
pending = 0U;
}
return (pending & 1U);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_ClearPending (IRQn_ID_t irqn)
\details This function clears the pending status of the interrupt identified by the irqn parameter.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_ClearPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority)
\details This function sets the priority of the interrupt identified by the irqn parameter.
Higher priority numbers have lower priority. The highest interrupt priority has priority value 0, while the lowest value
depends on the number of implemented priority levels.
The number of implemented priority bits can be determined by setting value \ref IRQ_PRIORITY_Msk to arbitrary irqn and by
retrieving the actual stored value with IRQ_GetPriority function.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_SetPriority ((IRQn_Type)irqn, priority);
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn uint32_t IRQ_GetPriority (IRQn_ID_t irqn)
\details This function retrieves the priority of the interrupt identified by the irqn parameter.
The valid priority value can be from zero (0) to the value of \ref IRQ_PRIORITY_Msk. \ref IRQ_PRIORITY_ERROR bit is set in
returned value for interrupts which cannot be identified by irqn.
For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
uint32_t priority;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
priority = GIC_GetPriority ((IRQn_Type)irqn);
} else {
priority = IRQ_PRIORITY_ERROR;
}
return (priority);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_SetPriorityMask (uint32_t priority)
\details This function sets the priority masking threshold for the current processor.
It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor.
Function returns error status -1 if priority masking is not supported.
For Arm GIC the default implementation looks like the following example:
\code
IRQ_SetPriorityMask (uint32_t priority) {
GIC_SetInterfacePriorityMask (priority);
return (0);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn uint32_t IRQ_GetPriorityMask (void)
\details This function retrieves the priority masking threshold for the current processor.
\ref IRQ_PRIORITY_ERROR value is returned if priority masking is not supported.
For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPriorityMask (void) {
return GIC_GetInterfacePriorityMask();
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn int32_t IRQ_SetPriorityGroupBits (uint32_t bits)
\details This function sets the number of MSB priority bits used to determine whether a pending interrupt has sufficient
priority to preempt a currently active interrupt.
The number of implemented group priority bits can be determined by setting value \ref IRQ_PRIORITY_Msk and by retrieving the
actual stored value with \ref IRQ_GetPriorityGroupBits function.
Function returns error status -1 if priority grouping is not supported.
For Arm GIC the default implementation looks like the following example:
\code
int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
int32_t status;
if (bits == IRQ_PRIORITY_Msk) {
bits = 7U;
}
if (bits < 8U) {
GIC_SetBinaryPoint (7U - bits);
status = 0;
} else {
status = -1;
}
return (status);
}
\endcode
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\fn uint32_t IRQ_GetPriorityGroupBits (void)
\details This function retrieves the number of MSB bits used to determine whether a pending interrupt has sufficient
priority to preempt a currently active interrupt.
\ref IRQ_PRIORITY_ERROR value is returned when priority grouping is not supported.
For Arm GIC the default implementation looks like the following example:
\code
uint32_t IRQ_GetPriorityGroupBits (void) {
uint32_t bp;
bp = GIC_GetBinaryPoint() & 0x07U;
return (7U - bp);
}
\endcode
*/
/** @} */ /* group irq_ctrl_gr */

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/* ########################## L1 Cache functions ################################# */
/**
\defgroup L1_cache_functions L1 Cache Functions
\ingroup CMSIS_Core_FunctionInterface
\brief L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache.
@{
\fn __STATIC_INLINE void L1C_EnableCaches(void)
\fn __STATIC_INLINE void L1C_DisableCaches(void)
\fn __STATIC_INLINE void L1C_EnableBTAC(void)
\fn __STATIC_INLINE void L1C_DisableBTAC(void)
\fn __STATIC_INLINE void L1C_InvalidateBTAC(void)
\fn __STATIC_INLINE void L1C_InvalidateICacheAll(void)
\fn __STATIC_INLINE void L1C_CleanDCacheMVA(void *va)
\fn __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va)
\fn __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va)
\fn __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op)
\details
Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
\fn __STATIC_INLINE void L1C_InvalidateDCacheAll(void)
\fn __STATIC_INLINE void L1C_CleanDCacheAll(void)
\fn __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void)
\fn __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op)
\details
Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
The parameter \b op defines which cleaning/invalidation strategy should be used:
- 0 - Cache is invalidated using DCISW register.
- 1 - Cache is cleaned using DCCSW register.
- other - Cache is invalidated and cleaned using DCCISW register.
@}
*/
/* ########################## L2 Cache functions ################################# */
/**
\defgroup L2_cache_functions L2C-310 Cache Controller Functions
\ingroup CMSIS_Core_FunctionInterface
\brief L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.\n
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/index.html">Level 2 Cache Controller L2C-310 Technical Reference Manual</a>.
*/
/** @{ */
/**
\struct L2C_310_TypeDef
\def L2C_310
\fn __STATIC_INLINE void L2C_Sync(void)
\fn __STATIC_INLINE int L2C_GetID (void)
\fn __STATIC_INLINE int L2C_GetType (void)
\fn __STATIC_INLINE void L2C_InvAllByWay (void)
\fn __STATIC_INLINE void L2C_CleanInvAllByWay (void)
\fn __STATIC_INLINE void L2C_Enable(void)
\fn __STATIC_INLINE void L2C_Disable(void)
\fn __STATIC_INLINE void L2C_InvPa (void *pa)
\fn __STATIC_INLINE void L2C_CleanPa (void *pa)
\fn __STATIC_INLINE void L2C_CleanInvPa (void *pa)
*/
/** @} */
/* ########################## L2C_310_TypeDef Member ########################## */
/**
\var L2C_310_TypeDef::ADDRESS_FILTER_END
\brief
\var __IOM uint32_t L2C_310_TypeDef::ADDRESS_FILTER_START
\brief
\var __IOM uint32_t L2C_310_TypeDef::AUX_CNT
\brief
\var __IM uint32_t L2C_310_TypeDef::CACHE_ID
\brief
\var __IOM uint32_t L2C_310_TypeDef::CACHE_SYNC
\brief
\var __IM uint32_t L2C_310_TypeDef::CACHE_TYPE
\brief
\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_INDEX_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_PA
\brief
\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_INDEX_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_PA
\brief
\var __IOM uint32_t L2C_310_TypeDef::CLEAN_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::CONTROL
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_0_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_1_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_2_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_3_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_4_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_5_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_6_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_7_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::DEBUG_CONTROL
\brief
\var __IOM uint32_t L2C_310_TypeDef::EVENT_CONTROL
\brief
\var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER0_CONF
\brief
\var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER1_CONF
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_0_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_1_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_2_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_3_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_4_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_5_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_6_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_7_WAY
\brief
\var __OM uint32_t L2C_310_TypeDef::INTERRUPT_CLEAR
\brief
\var __IOM uint32_t L2C_310_TypeDef::INTERRUPT_MASK
\brief
\var __IOM uint32_t L2C_310_TypeDef::INV_LINE_PA
\brief
\var __IOM uint32_t L2C_310_TypeDef::INV_WAY
\brief
\var __IOM uint32_t L2C_310_TypeDef::LOCK_LINE_EN
\brief
\var __IM uint32_t L2C_310_TypeDef::MASKED_INT_STATUS
\brief
\var __IM uint32_t L2C_310_TypeDef::RAW_INT_STATUS
\brief
\var __IOM uint32_t L2C_310_TypeDef::UNLOCK_ALL_BY_WAY
\brief
*/

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/* ########################## GIC functions ###################################### */
/**
\defgroup GIC_functions Generic Interrupt Controller Functions
\ingroup CMSIS_Core_FunctionInterface
\brief The Generic Interrupt Controller Functions grant access to the configuration, control and
status registers of the Generic Interrupt Controller (GIC).
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069c/index.html">Generic Interrupt Controller Architecture Specificaton</a>.
The following table shows the register naming of CMSIS in correlation with various technical reference manuals.
| CMSIS Register Name | Cortex-A5 TRM | Cortex-A7 TRM | Cortex-A9 TRM |
| :------------------------------------------------------------------- | :------------- | :--------------- | :------------- |
| <b>GIC Distributor</b> | | | |
| \ref GICDistributor_Type::CTLR "GICDistributor->CTLR" | ICDDCR | GICD_CTLR | ICDDCR |
| \ref GICDistributor_Type::TYPER "GICDistributor->TYPER" | ICDICTR | GICD_TYPER | ICDICTR |
| \ref GICDistributor_Type::IIDR "GICDistributor->IIDR" | ICDIIDR | GICD_IIDR | ICDIIDR |
| \ref GICDistributor_Type::STATUSR "GICDistributor->STATUSR" | | | |
| \ref GICDistributor_Type::SETSPI_NSR "GICDistributor->SETSPI_NSR" | | | |
| \ref GICDistributor_Type::CLRSPI_NSR "GICDistributor->CLRSPI_NSR" | | | |
| \ref GICDistributor_Type::IGROUPR "GICDistributor->IGROUPR[]" | ICDISR | GICD_IGROUPRn | ICDISRn |
| \ref GICDistributor_Type::ISENABLER "GICDistributor->ISENABLER[]" | ICDISER | GICD_ISENABLERn | ICDISERn |
| \ref GICDistributor_Type::ICENABLER "GICDistributor->ICENABLER[]" | ICDICER | GICD_ICENABLERn | ICDICERn |
| \ref GICDistributor_Type::ISPENDR "GICDistributor->ISPENDR[]" | ICDISPR | GICD_ISPENDRn | ICDISPRn |
| \ref GICDistributor_Type::ICPENDR "GICDistributor->ICPENDR[]" | ICDICPR | GICD_ICPENDRn | ICDICPRn |
| \ref GICDistributor_Type::ISACTIVER "GICDistributor->ISACTIVER[]" | ICDABR | GICD_ISACTIVERn | ICDABRn |
| \ref GICDistributor_Type::ICACTIVER "GICDistributor->ICACTIVER[]" | | GICD_ICACTIVERn | |
| \ref GICDistributor_Type::IPRIORITYR "GICDistributor->IPRIORITYR[]" | ICDIPR | GICD_IPRIORITYRn | ICDIPRn |
| \ref GICDistributor_Type::ITARGETSR "GICDistributor->ITARGETSR[]" | ICDIPTR | GICD_ITARGETSRn | ICDIPTRn |
| \ref GICDistributor_Type::ICFGR "GICDistributor->ICFGR[]" | ICDICFR | GICD_ICFGRn | ICDICFRn |
| \ref GICDistributor_Type::IGRPMODR "GICDistributor->IGRPMODR[0]" | ICDPPIS | GICD_PPISR | ppi_status |
| \ref GICDistributor_Type::IGRPMODR "GICDistributor->IGRPMODR[31:1]" | ICDSPIS | GICD_SPISRn | spi_status |
| \ref GICDistributor_Type::NSACR "GICDistributor->NSACR[]" | | | |
| \ref GICDistributor_Type::SGIR "GICDistributor->SGIR" | ICDSGIR | GICD_SGIR | ICDSGIR |
| \ref GICDistributor_Type::CPENDSGIR "GICDistributor->CPENDSGIR[]" | | GICD_CPENDSGIRn | |
| \ref GICDistributor_Type::SPENDSGIR "GICDistributor->SPENDSGIR[]" | | GICD_SPENDSGIRn | |
| \ref GICDistributor_Type::IROUTER "GICDistributor->IROUTER[]" | | | |
| <b>GIC Interface</b> | | | |
| \ref GICInterface_Type::CTLR "GICInterface->CTLR" | ICPICR | GICC_CTLR | ICCICR |
| \ref GICInterface_Type::PMR "GICInterface->PMR" | ICCIPMR | GICC_PMRn | ICCPMR |
| \ref GICInterface_Type::BPR "GICInterface->BPR" | ICCBPR | GICC_BPR | ICCBPR |
| \ref GICInterface_Type::IAR "GICInterface->IAR" | ICCIAR | GICC_IAR | ICCIAR |
| \ref GICInterface_Type::EOIR "GICInterface->EOIR" | ICCEOIR | GICC_EOIR | ICCEOIR |
| \ref GICInterface_Type::RPR "GICInterface->RPR" | ICCRPR | GICC_RPR | ICCRPR |
| \ref GICInterface_Type::HPPIR "GICInterface->HPPIR" | ICCHPIR | GICC_HPPIR | ICCHPIR |
| \ref GICInterface_Type::ABPR "GICInterface->ABPR" | ICCABPR | GICC_ABPR | ICCABPR |
| \ref GICInterface_Type::AIAR "GICInterface->AIAR" | | GICC_AIAR | |
| \ref GICInterface_Type::AEOIR "GICInterface->AEOIR" | | GICC_AEOIR | |
| \ref GICInterface_Type::AHPPIR "GICInterface->AHPPIR" | | GICC_AHPPIR | |
| \ref GICInterface_Type::STATUSR "GICInterface->STATUSR" | | | |
| \ref GICInterface_Type::APR "GICInterface->APR[]" | | GICC_APR0 | |
| \ref GICInterface_Type::NSAPR "GICInterface->NSAPR[]" | | GICC_NSAPR0 | |
| \ref GICInterface_Type::IIDR "GICInterface->IIDR" | ICCIIDR | GICC_IIDR | ICCIDR |
| \ref GICInterface_Type::DIR "GICInterface->DIR" | | GICC_DIR | |
*/
/** @{ */
/**
\fn __STATIC_INLINE void GIC_EnableDistributor(void)
\details Globally enable the forwarding of interrupts to the CPU interfaces.
\fn __STATIC_INLINE void GIC_DisableDistributor(void)
\details Globally disable the forwarding of interrupts to the CPU interfaces.
\see GIC_EnableDistributor
\fn __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
\details
Provides information about the configuration of the GIC. It indicates:
- whether the GIC implements the Security Extensions
- the maximum number of interrupt IDs that the GIC supports
- the number of CPU interfaces implemented
- if the GIC implements the Security Extensions, the maximum number of
implemented Lockable Shared Peripheral Interrupts (LSPIs).
\fn __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
\details
Provides information about the implementer and revision of the Distributor.
\fn __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
\details
The \ref GICDistributor_Type.ITARGETSR "ITARGETSR" registers provide an 8-bit CPU targets field
for each interrupt supported by the GIC. This field stores the list of target processors for the
interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the
interrupt if it is asserted and has sufficient priority.
\fn __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
\details
Read the current interrupt to CPU assignment for the given interrupt.
\see GIC_SetTarget
\fn __STATIC_INLINE void GIC_EnableInterface(void)
\details
Sets the Enable bit in the local CPUs \ref GICInterface_Type.CTLR "CTLR" register.
Only the CPU executing the call is affected.
\fn __STATIC_INLINE void GIC_DisableInterface(void)
\details
Resets the Enable bit in the local CPUs \ref GICInterface_Type.CTLR "CTLR" register.
Only the CPU executing the call is affected.
\fn __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
\details
Provides the interrupt number of the highest priority interrupt pending.
A read of this register acts as an acknowledge for the interrupt.
The read returns a spurious interrupt number of 1023 if any of the following apply:
- Forwarding of interrupts by the Distributor to the CPU interface is disabled.
- Signaling of interrupts by the CPU interface to the connected PE is disabled.
- There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.
\see GIC_EndInterrupt
\fn __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
A write to this register performs priority drop for the specified interrupt.
For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt
acknowledgement, i.e. calls to \ref GIC_AcknowledgePending. Behavior is UNPREDICTABLE if:
- This ordering constraint is not maintained.
- The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.
- The given interrupt number does not match the last valid interrupt value returned by \ref GIC_AcknowledgePending.
\fn __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
\details
Enables forwarding of the corresponding interrupt to the CPU interfaces.
\fn __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
\details
Disables forwarding of the corresponding interrupt to the CPU interfaces.
\fn __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
\details
Adds the pending state to the corresponding interrupt.
\fn __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
\details
Removes the pending state from the corresponding interrupt.
\fn __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\details
Configures the priority of the given interrupt.
The available interrupt priorities are IMPLEMENTATION DEFINED. In order to
query the actual priorities one can
\code
GIC_SetPriority(IRQn_TIM1, UINT32_MAX); // try to configure lowest possible priority
uint32_t actual = GIC_GetPriority(IRQn_TIM1); // retrieve actual lowest priority usable
\endcode
\fn __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
\details
Can be used to retrieve the actual priority depending on the GIC implementation.
\see GIC_SetPriority
\fn __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
\details
Only interrupts with a higher priority (lower values) than the value provided are signaled.
\fn __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
\see GIC_SetInterfacePriorityMask
\fn __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
\details
The binary point defines the amount of priority bits used as a group priority and subpriorities.
Interrupts sharing the same group priority do not preempt each other. But interrupts having a
higher group priority (lower value) preempt interrups with a lower group priority.
The subpriority defines the execution sequence of interrupts with the same group priority if
multiple are pending at time.
\fn __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
\details
\see GIC_SetBinaryPoint
\fn __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
\details
The return value is a combination of GIC's \ref GICDistributor_Type::ISACTIVER "ISACTIVER"
and \ref GICDistributor_Type::ISPENDR "ISPENDR" registers.
Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts
active bit (interrupt is currently handled).
\fn __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
\fn __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
\fn __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
\fn __STATIC_INLINE void GIC_DistInit(void)
\details
All shared peripheral interrupts (SPIs) are initialized to be
- disabled
- level-sensitive, 1-N model
- priority 0x7F
- targeting CPU0
and the distributor is enabled.
\see
GIC_DisableIRQ\n
GIC_SetLevelModel\n
GIC_SetPriority\n
GIC_SetTarget\n
GIC_EnableDistributor
\fn __STATIC_INLINE void GIC_CPUInterfaceInit(void)
\details
All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be
- disabled
- level-sensitive, 1-N model
- priority 0x7F
and the interrupt interface is enabled.
The binary point is set to zero.
The interrupt priority mask is set to 0xFF.
\see
GIC_DisableIRQ\n
GIC_SetLevelModel\n
GIC_SetPriority\n
GIC_EnableInterface\n
GIC_SetBinaryPoint\n
GIC_SetInterfacePriorityMask\n
\fn __STATIC_INLINE void GIC_Enable(void)
\details
Initializes the distributor and the cpu interface.
\see
GIC_DistInit
GIC_CPUInterfaceInit
*/
/**
\def GICDistributor
\details
Use GICDistributor to access the GIC Distributor registers.
\b Example:
\code
GICDistributor->CTRL |= 1; // Enable group 0 interrupts
\endcode
*/
/**
\def GICInterface
\details
Use GICInterface to access the GIC Interface registers.
\b Example:
\code
GICInterface->CTLR |= 1; // Enable interrupt signaling
\endcode
*/
/**
\struct GICInterface_Type
\struct GICDistributor_Type
*/
/** @} */
/* ########################## GICInterface_Type Member ########################## */
/**
\var __IOM uint32_t GICInterface_Type::CTLR
\details CPU Interface Control Register
Enables the signaling of interrupts by the CPU interface to the connected processor, and
provides additional top-level control of the CPU interface. In a GICv2 implementation, this
includes control of the end of interrupt (EOI) behavior.
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:1] | - | Reserved. |
| [0] | Enable | Interrupt signaling: 0 - Disable. 1 - Enable. |
\var __IM uint32_t GICInterface_Type::IAR
\details CPU Interface Interrupt Acknowledge Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:24] | - | Reserved. |
| [23:0] | INTID | The interrupt number of the signaled interrupt. |
\var __OM uint32_t GICInterface_Type::EOIR
\details CPU Interface End Of Interrupt Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:24] | - | Reserved. |
| [23:0] | INTID | The interrupt number of the finished interrupt. |
\var __IM uint32_t GICInterface_Type::HPPIR
\details CPU Interface Highest Priority Pending Interrupt Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:24] | - | Reserved. |
| [23:0] | INTID | The INTID of the signaled interrupt. |
\var __IM uint32_t GICInterface_Type::IIDR
\details CPU Interface Identification Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:20] | ProductID | An IMPLEMENTATION DEFINED product identifier |
| [19:16] | Arch_version | The version of the GIC architecture that is implemented. |
| [15:12] | Revision | An IMPLEMENTATION DEFINED revision number for the CPU interface. |
| [11:0] | Implementer | Contains the JEP106 code of the company that implemented the CPU interface. |
\var __IOM uint32_t GICInterface_Type::PMR
\details CPU Interface Priority Mask Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:8] | - | Reserved. |
| [7:0] | Priority | The priority mask level for the CPU interface. |
\note IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.
\var __IOM uint32_t GICInterface_Type::BPR
\details CPU Interface Binary Point Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:3] | - | Reserved. |
| [2:0] | Binary_Point | Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. |
The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please
refer to the section Interrupt prioritization in the
<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a>
for details.
\var __IOM uint32_t GICInterface_Type::ABPR
\details CPU Interface Aliased Binary Point Register
\see GICInterface_Type::BPR
\var __OM uint32_t GICInterface_Type::AEOIR
\details CPU Interface Aliased End Of Interrupt Register
\see GICInterface_Type::EOIR
\var __IM uint32_t GICInterface_Type::AHPPIR
\details CPU Interface Aliased Highest Priority Pending Interrupt Register
\see GICInterface_Type::HPPIR
\var __IM uint32_t GICInterface_Type::AIAR
\details CPU Interface Aliased Interrupt Acknowledge Register
\see GICInterface_Type::IAR
\var __IOM uint32_t GICInterface_Type::APR[4]
\details CPU Interface Active Priorities Registers
\note The register values are IMPLEMENTATION DEFINED.
\var __OM uint32_t GICInterface_Type::DIR
\details CPU Interface Deactivate Interrupt Register
| Bits | Name | Function |
| :------ | :---- | :------------------------------------------------------------- |
| [31:24] | - | Reserved. |
| [23:0] | INTID | The INTID of the interrupt to be disabled. |
\var __IOM uint32_t GICInterface_Type::NSAPR[4]
\details CPU Interface Non-secure Active Priorities Registers
\note The register values are IMPLEMENTATION DEFINED.
\see GICInterface_Type::APR[4]
\var __IM uint32_t GICInterface_Type::RPR
\details CPU Interface Running Priority Register
| Bits | Name | Function |
| :------ | :------- | :------------------------------------------------------------- |
| [31:8] | - | Reserved. |
| [7:0] | Priority | The current running priority on the CPU interface. |
\var __IOM uint32_t GICInterface_Type::STATUSR
\details CPU Interface Status Register
| Bits | Name | Function |
| :------ | :------- | :------------------------------------------------------------- |
| [31:5] | - | Reserved. |
| [4] | ASV | Attempted security violation. |
| [3] | WROD | Write to an RO location. |
| [2] | RWOD | Read of a WO location. |
| [1] | WRD | Write to a reserved location. |
| [0] | RRD | Read of a reserved location. |
*/
/* ########################## GICDistributor_Type Member ########################## */
/**
\var __IOM uint32_t GICDistributor_Type::CTLR
\details Distributor Control Register
When access is Secure, in a system that supports two Security states:
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31] | RWP | Indicates whether a register write is in progress or not. |
| [30:8] | - | Reserved. |
| [7] | EINWF | Enable 1 of N Wakeup Functionality, if available. |
| [6] | DS | Disable Security. |
| [5] | ARE_NS | Affinity Routing Enable, Non-secure state. |
| [4] | ARE_S | Affinity Routing Enable, Secure state. |
| [3] | - | Reserved. |
| [2] | EnableGrp1S | Enable Secure Group 1 interrupts. |
| [1] | EnableGrp1NS | Enable Non-secure Group 1 interrupts. |
| [0] | EnableGrp0 | Enable Group 0 interrupts. |
When access is Non-secure, in a system that supports two Security states:
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31] | RWP | Indicates whether a register write is in progress or not. |
| [30:5] | - | Reserved. |
| [4] | ARE_NS | Affinity Routing Enable, Non-secure state. |
| [3:2] | - | Reserved. |
| [1] | EnableGrp1A | Enable Non-secure Group 1 interrupts. |
| [0] | EnableGrp1 | Enable Non-secure Group 1 interrupts. |
When in a system that supports only a single Security state:
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31] | RWP | Indicates whether a register write is in progress or not. |
| [30:8] | - | Reserved. |
| [7] | EINWF | Enable 1 of N Wakeup Functionality, if available. |
| [6] | DS | Disable Security. |
| [5] | - | Reserved. |
| [4] | ARE | Affinity Routing Enable. |
| [3:2] | - | Reserved. |
| [1] | EnableGrp1 | Enable Group 1 interrupts. |
| [0] | EnableGrp0 | Enable Group 0 interrupts. |
\var __IM uint32_t GICDistributor_Type::TYPER
\details Interrupt Controller Type Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:16] | - | Reserved. |
| [15:11] | LSPI | Maximum number of lockable shared interrupts. |
| [10] | SecurityExtn | Security Extensions: 0 - not implemented. 1 - implemented. |
| [9:8] | - | Reserved. |
| [7:5] | CPUNumber | Number of implemented CPU interfaces [=CPUNumber+1] |
| [4:0] | ITLinesNumber | Maximum number of interrups supported [=32*(ITLinesNumber+1)]. |
\var __IM uint32_t GICDistributor_Type::IIDR
\details Distributor Implementer Identification Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:24] | ProductID | An IMPLEMENTATION DEFINED product identifier |
| [23:20] | - | Reserved. |
| [19:16] | Variant | An IMPLEMENTATION DEFINED variant number. |
| [15:12] | Revision | An IMPLEMENTATION DEFINED revision number. |
| [11:0] | Implementer | Contains the JEP106 code of the company implemented the GICD. |
\var __IOM uint8_t GICDistributor_Type::ITARGETSR[1020]
\details Interrupt Processor Targets Registers
Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds
to an unimplemented CPU interface is RAZ/WI.
| CPU target field value | Interrupt targets |
| :--------------------- | :---------------- |
| 0bxxxxxxx1 | CPU interface 0 |
| 0bxxxxxx1x | CPU interface 1 |
| 0bxxxxx1xx | CPU interface 2 |
| 0bxxxx1xxx | CPU interface 3 |
| 0bxxx1xxxx | CPU interface 4 |
| 0bxx1xxxxx | CPU interface 5 |
| 0bx1xxxxxx | CPU interface 6 |
| 0b1xxxxxxx | CPU interface 7 |
\var __IOM uint32_t GICDistributor_Type::IGROUPR[32]
\details Interrupt Group Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
And the value denotes:
- 0 When \ref GICDistributor_Type::CTLR "CTLR".DS==1, the corresponding interrupt is Group 0\n
When \ref GICDistributor_Type::CTLR "CTLR".DS==0, the corresponding interrupt is Secure.
- 1 When \ref GICDistributor_Type::CTLR "CTLR".DS==1, the corresponding interrupt is Group 1.\n
When \ref GICDistributor_Type::CTLR "CTLR".DS==0, the corresponding interrupt is Non-secure Group 1.
\var __IO uint32_t GICDistributor_Type::CLRSPI_NSR
\details Clear Non-secure SPI Pending Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------ |
| [31:10] | - | Reserved. |
| [9:0] | INTID | The interrupt number to clear pending state from. |
\var __IO uint32_t GICDistributor_Type::CLRSPI_SR
\details Clear Secure SPI Pending Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------ |
| [31:10] | - | Reserved. |
| [9:0] | INTID | The interrupt number to clear pending state from. |
\var __IOM uint32_t GICDistributor_Type::IGRPMODR[32]
\details Interrupt Group Modifier Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
\var __IOM uint64_t GICDistributor_Type::IROUTER[988]
\details Interrupt Routing Registers
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------ |
| [63:40] | - | Reserved. |
| [39:32] | Aff3 | Affinity level 3, the least significant affinity level field. |
| [31] | IRM | Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. |
| [30:24] | - | Reserved. |
| [23:16] | Aff2 | Affinity level 2, an intermediate affinity level field. |
| [15:8] | Aff1 | Affinity level 1, an intermediate affinity level field. |
| [7:0] | Aff0 | Affinity level 0, the most significant affinity level field. |
\var __IOM uint32_t GICDistributor_Type::NSACR[64]
\details Non-secure Access Control Registers
Each two bits corresponds to one interrupt:
- Register index is given by INTID/16
- Bit number is given by 2*INTID%16
The possible values of each 2-bit field are:
- 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
- 01 - Non-secure accesses are only permitted to requesting fields.
- 10 - As 01, additionally accesses to clearing field are permitted.
- 11 - As 10, additionally accesses to target and routing fields are permitted.
\var __IO uint32_t GICDistributor_Type::SETSPI_NSR
\details Set Non-secure SPI Pending Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------ |
| [31:10] | - | Reserved. |
| [9:0] | INTID | The interrupt number to set pending state for. |
\var __IO uint32_t GICDistributor_Type::SETSPI_SR
\details Set Secure SPI Pending Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------ |
| [31:10] | - | Reserved. |
| [9:0] | INTID | The interrupt number to set pending state for. |
\var __IOM uint8_t GICDistributor_Type::SPENDSGIR[16]
\details SGI Set-Pending Registers
Each register corresponds to one software generated interrupt (SGI).
Reading from this register reveals
- 0 - interrupt is not pending
- 1 - interrupt is pending
Writing to this register causes
- 0 - no effect
- 1 - adds the pending state
\var __IOM uint8_t GICDistributor_Type::CPENDSGIR[16]
\details SGI Clear-Pending Registers
Each register corresponds to one software generated interrupt (SGI).
Reading from this register reveals
- 0 - interrupt is not pending
- 1 - interrupt is pending
Writing to this register causes
- 0 - no effect
- 1 - removes the pending state
\var __IOM uint32_t GICDistributor_Type::STATUSR
\details Error Reporting Status Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------ |
| [31:4] | - | Reserved. |
| [3] | WROD | Write to an RO location. |
| [2] | RWOD | Read of a WO location. |
| [1] | WRD | Write to a reserved location. |
| [0] | RRD | Read of a reserved location. |
\var __IOM uint32_t GICDistributor_Type::ISENABLER[32]
\details Interrupt Set-Enable Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
\note Bits corresponding to unimplemented interrupts are RAZ/WI.
\var __IOM uint32_t GICDistributor_Type::ICENABLER[32]
\details Interrupt Clear-Enable Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
\note Bits corresponding to unimplemented interrupts are RAZ/WI.
\var __IOM uint32_t GICDistributor_Type::ISPENDR[32]
\details Interrupt Set-Pending Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
\note Bits corresponding to unimplemented interrupts are RAZ/WI.
\var __IOM uint32_t GICDistributor_Type::ICPENDR[32]
\details Interrupt Clear-Pending Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
\note Bits corresponding to unimplemented interrupts are RAZ/WI.
\var __IOM uint32_t GICDistributor_Type::ICFGR[64]
\details Interrupt Configuration Registers
Each interrupt can be configured by two corresponding bits:
| Bits | Name | Function |
| :------------- | :------------ | :------------------------------------------------------------- |
| [2*INTID%16+1] | Edge | Interrupt is: 0 - level sensitive, 1 - edge triggered |
| [2*INTID%16] | Model | 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported |
\var __IOM uint8_t GICDistributor_Type::IPRIORITYR[1020]
\details Interrupt Priority Registers
A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each
field. In each field, unimplemented bits are RAZ/WI.
\note A register field corresponding to an unimplemented interrupt is RAZ/WI.
\var __IOM uint32_t GICDistributor_Type::ISACTIVER[32]
\details Interrupt Set-Active Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
\note Bits corresponding to unimplemented interrupts are RAZ/WI.
\var __IOM uint32_t GICDistributor_Type::ICACTIVER[32]
\details Interrupt Clear-Active Registers
Each bit corresponds to one interrupt:
- Register index is given by INTID/32
- Bit number is given by INTID%32
\note Bits corresponding to unimplemented interrupts are RAZ/WI.
\var __OM uint32_t GICDistributor_Type::SGIR
\details Software Generated Interrupt Register
| Bits | Name | Function |
| :------ | :------------ | :--------------------------------------------------------------- |
| [31:26] | - | Reserved. |
| [25:24] | TargetFilterList | Determines how the Distributor processes the requested SGI. |
| [23:16] | CPUTargetList | When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. |
| [15] | NSATT | Specifies the required group of the SGI. |
| [14:4] | - | Reserved. |
| [3:0] | INTID | The INTID of the SGI to forward to the specified CPU interfaces. |
Refer to \ref GICDistributor_Type::ITARGETSR "ITARGETSR" for details on TargetFilterList field.
*/

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/* ########################## MMU functions ###################################### */
/**
\defgroup MMU_functions Memory Management Unit Functions
\ingroup CMSIS_Core_FunctionInterface
\brief MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.\n
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.
*/
/** @{ */
/**
\fn __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
\details
The function sets section execution-never attribute
\fn __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
\details
The function sets section domain.
\fn __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
\details
The function sets section parity check
\fn __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
\details
The function sets section access privileges
\fn __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
\details
The function sets section shareability
\fn __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
\details
The function sets section Global attribute
\fn __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
\details
The function sets section Global attribute
\fn __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
\details
The function sets 4k/64k page execution-never attribute
\fn __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
\details
The function sets 4k/64k page domain
\fn __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
\details
The function sets 4k/64k page parity check
\fn __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
\details
The function sets 4k/64k page access privileges
\fn __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
\details
The function sets 4k/64k page shareability
\fn __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
\details
The function sets 4k/64k page Global attribute
\fn __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
\details
The function sets 4k/64k page Global attribute
\fn __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
\details
The function sets section memory attributes
\fn __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
\details
The function sets 4k/64k page memory attributes
\fn __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
\details
The function creates a section descriptor.
\fn __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
\details
The function creates a 4k/64k page descriptor.
Assumptions:
- TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- Functions always return 0
\fn __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
\fn __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
\fn __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
\fn __STATIC_INLINE void MMU_Enable(void)
\details
Set M bit 0 to enable the MMU
Set AFE bit to enable simplified access permissions model
Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
\fn __STATIC_INLINE void MMU_Disable(void)
\fn __STATIC_INLINE void MMU_InvalidateTLB(void)
*/
/** @} */
/* end of MMU_functions */
/**
\defgroup MMU_defs_gr MMU Defines and Structs
\ingroup MMU_functions
\brief Defines and structures that relate to the Memory Management Unit
*/
/** @{ */
/**
\def SECTION_DESCRIPTOR
\def SECTION_B_SHIFT
\def SECTION_C_SHIFT
\def SECTION_TEX0_SHIFT
\def SECTION_TEX1_SHIFT
\def SECTION_TEX2_SHIFT
\def SECTION_XN_SHIFT
\def SECTION_DOMAIN_SHIFT
\def SECTION_P_SHIFT
\def SECTION_AP_SHIFT
\def SECTION_AP2_SHIFT
\def SECTION_S_SHIFT
\def SECTION_NG_SHIFT
\def SECTION_NS_SHIFT
\def PAGE_L1_DESCRIPTOR
\def PAGE_L2_4K_DESC
\def PAGE_L2_64K_DESC
\def PAGE_4K_B_SHIFT
\def PAGE_4K_C_SHIFT
\def PAGE_4K_TEX0_SHIFT
\def PAGE_4K_TEX1_SHIFT
\def PAGE_4K_TEX2_SHIFT
\def PAGE_64K_B_SHIFT
\def PAGE_64K_C_SHIFT
\def PAGE_64K_TEX0_SHIFT
\def PAGE_64K_TEX1_SHIFT
\def PAGE_64K_TEX2_SHIFT
\def PAGE_B_SHIFT
\def PAGE_C_SHIFT
\def PAGE_TEX_SHIFT
\def PAGE_XN_4K_SHIFT
\def PAGE_XN_64K_SHIFT
\def PAGE_DOMAIN_SHIFT
\def PAGE_P_SHIFT
\def PAGE_AP_SHIFT
\def PAGE_AP2_SHIFT
\def PAGE_S_SHIFT
\def PAGE_NG_SHIFT
\def PAGE_NS_SHIFT
\def OFFSET_1M
\def OFFSET_64K
\def OFFSET_4K
\def DESCRIPTOR_FAULT
\enum mmu_region_size_Type
\enum mmu_memory_Type
\enum mmu_cacheability_Type
\enum mmu_ecc_check_Type
\enum mmu_execute_Type
\enum mmu_global_Type
\enum mmu_shared_Type
\enum mmu_secure_Type
\enum mmu_access_Type
\struct mmu_region_attributes_Type
\def section_normal(descriptor_l1, region)
\def section_normal_cod(descriptor_l1, region)
\def section_normal_ro(descriptor_l1, region)
\def section_normal_rw(descriptor_l1, region)
\def section_so(descriptor_l1, region)
\def section_device_ro(descriptor_l1, region)
\def section_device_rw(descriptor_l1, region)
\def page4k_device_rw(descriptor_l1, descriptor_l2, region)
\def page64k_device_rw(descriptor_l1, descriptor_l2, region)
*/
/** @} */
/* end group MMU_defs_gr */

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/* ########################## Generic Physical Timer functions ############################ */
/**
\defgroup PL1_timer_functions Generic Physical Timer Functions
\ingroup CMSIS_Core_FunctionInterface
\brief Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.\n
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html">Cortex-A7 MPCore Technical Reference Manual</a>.
*/
/** @{ */
/** \brief Physical Timer Control register */
typedef union
{
struct
{
uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
uint32_t _reserved0:29; /*!< \brief bit: 3..31 Reserved */
} b; /*!< \brief Structure used for bit access */
uint32_t w; /*!< \brief Type used for word access */
} CNTP_CTL_Type;
/** Configures the frequency the timer shall run at.
* \param value The timer frequency in Hz.
*/
__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value);
/** Sets the reset value of the timer.
* \param value The value the timer is loaded with.
*/
__STATIC_INLINE void PL1_SetLoadValue(uint32_t value);
/** Get the current counter value.
* \return Current counter value.
*/
__STATIC_INLINE uint32_t PL1_GetCurrentValue();
/** \brief Get the current physical counter value.
* \return Current physical counter value.
*/
__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void);
/** \brief Set the physical compare value.
* \param [in] value New physical timer compare value.
*/
__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value);
/** \brief Get the physical compare value.
* \return Physical compare value.
*/
__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void);
/** Configure the timer by setting the control value.
* \param value New \ref CNTP_CTL_Type "timer control value".
*/
__STATIC_INLINE void PL1_SetControl(uint32_t value);
/** Get the timer control value.
* \return \ref CNTP_CTL_Type Timer control value.
*/
__STATIC_INLINE uint32_t PL1_GetControl();
/** @} */
/* ########################## Private Timer functions ############################ */
/**
\defgroup PTM_timer_functions Private Timer Functions
\ingroup CMSIS_Core_FunctionInterface
\brief Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.\n
References: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0434c/index.html">Cortex-A5 MPCore Technical Reference Manual</a>,
<a href="http://infocenter.arm.com/help/topic/com.arm.doc.100486_0401_10_en/index.html">Cortex-A9 MPCore Technical Reference Manual</a>.
@{
\struct Timer_Type
\def PTIM
\fn __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
\fn __STATIC_INLINE uint32_t PTIM_GetLoadValue()
\fn __STATIC_INLINE uint32_t PTIM_GetCurrentValue()
\fn __STATIC_INLINE void PTIM_SetControl(uint32_t value)
\fn __STATIC_INLINE uint32_t PTIM_GetControl(void)
\fn __STATIC_INLINE void PTIM_ClearEventFlag(void)
@}
*/
/* ########################## Timer_Type Members ########################## */
/**
\var __IOM uint32_t Timer_Type::LOAD
\details Private Timer Load Register
The Timer Load Register contains the value copied to the Timer Counter Register when
it decrements down to zero with auto reload mode enabled. Writing to the Timer Load
Register means that you also write to the Timer Counter Register.
\var __IOM uint32_t Timer_Type::COUNTER
\details Private Timer Counter Register
The Timer Counter Register is a decrementing counter.
The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register.
When the Timer Counter Register reaches zero and auto reload mode is enabled, it
reloads the value in the Timer Load Register and then decrements from that value. If
auto reload mode is not enabled, the Timer Counter Register decrements down to zero
and stops.
When the Timer Counter Register reaches zero, the timer interrupt status event flag is
set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt
generation is enabled in the Timer Control Register.
Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter
Register to decrement from the newly written value.
\var __IOM uint32_t Timer_Type::CONTROL
\details Private Timer Control Register
| Bits | Name | Function |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:16] | - | Reserved. |
| [15:8] | Prescaler | The prescaler modifies the clock period for the decrementing event for the Counter Register. |
| [7:3] | - | Reserved. |
| [2] | IRQ Enable | If set, the interrupt is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. |
| [1] | Auto Reload | If set, each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register. |
| [0] | Time Enabled | If set, Timer is enabled and the counter decrements normally. |
\var __IM uint32_t Timer_Type::ISR
\details Private Timer Interrupt Status Register
The event flag is a sticky bit that is automatically set when the Counter Register reaches
zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt
Distributor after the event flag is set. The event flag is cleared when written to 1.
\var __IOM uint32_t Timer_Type::WLOAD
\details Watchdog Load Register
The Watchdog Load Register contains the value copied to the Watchdog Counter
Register when it decrements down to zero with auto reload mode enabled, in Timer
mode. Writing to the Watchdog Load Register means that you also write to the
Watchdog Counter Register.
\var __IOM uint32_t Timer_Type::WCOUNTER
\details Watchdog Counter Register
The Watchdog Counter Register is a down counter.
The behavior of the watchdog when the Watchdog Counter Register reaches zero
depends on its current mode:
- Timer mode: The watchdog interrupt status event flag is set and the interrupt
is set as pending in the Interrupt Distributor.
- Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ
reset request output pin is asserted.
\var __IOM uint32_t Timer_Type::WCONTROL
\details Watchdog Control Register
| Bits | Name | Function |
| :------ | :-------------- | :------------------------------------------------------------- |
| [31:16] | - | Reserved. |
| [15:8] | Prescaler | The prescaler modifies the clock period for the decrementing event for the Counter Register. |
| [7:4] | - | Reserved. |
| [3] | Watchdog Mode | 0 - Timer mode (default), 1 - Watchdog mode |
| [2] | IT Enable | Interrupt enable for timer mode. |
| [1] | Auto Reload | 0 - Single shot mode, 1 - Continuous timer mode |
| [0] | Watchdog Enable | 0 - Watchdog counter disabled, 1 - Watchdog timer enabled |
\var __IOM uint32_t Timer_Type::WISR
\details Watchdog Interrupt Status Register
| Bits | Name | Function |
| :------ | :-------------- | :------------------------------------------------------------- |
| [31:1] | - | Reserved. |
| [0] | Event Flag | The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. |
\var __IOM uint32_t Timer_Type::WRESET
\details Watchdog Reset Status Register
| Bits | Name | Function |
| :------ | :-------------- | :------------------------------------------------------------- |
| [31:1] | - | Reserved. |
| [0] | Reset Flag | The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode) |
\var __IM uint32_t Timer_Type::WDISABLE
\details Watchdog Disable Register
Use the Watchdog Disable Register to switch from watchdog to timer mode. The
software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable
Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.
*/
/* ########################## Private Timer Member ########################## */
/**
\var uint32_t CNTP_CTL_Type::ENABLE
\details Enables the timer.
Permitted values are:
- 0 - Timer disabled.
- 1 - Timer enabled.
\var uint32_t CNTP_CTL_Type::IMASK
\details Timer output signal mask bit.
Permitted values are:
- 0 - Timer output signal is not masked.
- 1 - Timer output signal is masked.
\var uint32_t CNTP_CTL_Type::ISTATUS
\details The status of the timer.
This bit indicates whether the timer condition is asserted:
- 0 - Timer condition is not asserted.
- 1 - Timer condition is asserted.
*/