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280
CMSIS_5-develop/CMSIS/RTOS/RTX/SRC/rt_HAL_CM.h
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280
CMSIS_5-develop/CMSIS/RTOS/RTX/SRC/rt_HAL_CM.h
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/*----------------------------------------------------------------------------
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* CMSIS-RTOS - RTX
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*----------------------------------------------------------------------------
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* Name: RT_HAL_CM.H
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* Purpose: Hardware Abstraction Layer for Cortex-M definitions
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* Rev.: V4.79
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*----------------------------------------------------------------------------
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*
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* Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*---------------------------------------------------------------------------*/
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/* Definitions */
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#define INITIAL_xPSR 0x01000000U
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#define DEMCR_TRCENA 0x01000000U
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#define ITM_ITMENA 0x00000001U
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#define MAGIC_WORD 0xE25A2EA5U
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#define MAGIC_PATTERN 0xCCCCCCCCU
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#if defined (__CC_ARM) /* ARM Compiler */
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#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) && !defined(NO_EXCLUSIVE_ACCESS))
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#define __USE_EXCLUSIVE_ACCESS
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#else
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#undef __USE_EXCLUSIVE_ACCESS
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#endif
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#ifndef __CMSIS_GENERIC
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#define __DMB() do {\
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__schedule_barrier();\
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__dmb(0xF);\
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__schedule_barrier();\
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} while (0)
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#endif
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#elif defined (__GNUC__) /* GNU Compiler */
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#undef __USE_EXCLUSIVE_ACCESS
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#if defined (__CORTEX_M0)
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#define __TARGET_ARCH_6S_M
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#endif
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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#define __TARGET_FPU_VFP
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#endif
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#define __inline inline
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#define __weak __attribute__((weak))
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#ifndef __CMSIS_GENERIC
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__attribute__((always_inline)) static inline void __enable_irq(void)
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{
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__asm volatile ("cpsie i");
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}
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__attribute__((always_inline)) static inline U32 __disable_irq(void)
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{
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U32 result;
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__asm volatile ("mrs %0, primask" : "=r" (result));
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__asm volatile ("cpsid i");
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return(result & 1);
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}
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__attribute__((always_inline)) static inline void __DMB(void)
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{
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__asm volatile ("dmb 0xF":::"memory");
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}
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#endif
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__attribute__(( always_inline)) static inline U8 __clz(U32 value)
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{
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U8 result;
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__asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
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return(result);
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}
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#elif defined (__ICCARM__) /* IAR Compiler */
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#undef __USE_EXCLUSIVE_ACCESS
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#if (__CORE__ == __ARM6M__)
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#define __TARGET_ARCH_6S_M 1
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#endif
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#if defined __ARMVFP__
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#define __TARGET_FPU_VFP 1
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#endif
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#define __inline inline
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#ifndef __CMSIS_GENERIC
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static inline void __enable_irq(void)
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{
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__asm volatile ("cpsie i");
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}
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static inline U32 __disable_irq(void)
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{
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U32 result;
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__asm volatile ("mrs %0, primask" : "=r" (result));
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__asm volatile ("cpsid i");
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return(result & 1);
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}
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#endif
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static inline U8 __clz(U32 value)
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{
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U8 result;
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__asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
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return(result);
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}
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#endif
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/* NVIC registers */
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#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010U))
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#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014U))
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#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018U))
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#define NVIC_ISER ((volatile U32 *)0xE000E100U)
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#define NVIC_ICER ((volatile U32 *)0xE000E180U)
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#if defined(__TARGET_ARCH_6S_M)
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#define NVIC_IP ((volatile U32 *)0xE000E400U)
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#else
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#define NVIC_IP ((volatile U8 *)0xE000E400U)
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#endif
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#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04U))
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#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0CU))
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#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1CU))
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#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20U))
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#define OS_PEND_IRQ() NVIC_INT_CTRL = (1UL<<28)
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#define OS_PENDING ((NVIC_INT_CTRL >> 26) & 5U)
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#define OS_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_PENDING) << 25
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#define OS_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | (U8)(p<<2)) << 26
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#define OS_LOCK() NVIC_ST_CTRL = 0x0005U
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#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007U
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#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1U)
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#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_X_PENDING) << 27
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#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | p) << 28
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#if defined(__TARGET_ARCH_6S_M)
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#define OS_X_INIT(n) NVIC_IP[n>>2] |= (U32)0xFFU << ((n & 0x03U) << 3); \
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NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
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#else
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#define OS_X_INIT(n) NVIC_IP[n] = 0xFFU; \
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NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
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#endif
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#define OS_X_LOCK(n) NVIC_ICER[n>>5] = (U32)1U << (n & 0x1FU)
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#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
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/* Core Debug registers */
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#define DEMCR (*((volatile U32 *)0xE000EDFCU))
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/* ITM registers */
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#define ITM_CONTROL (*((volatile U32 *)0xE0000E80U))
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#define ITM_ENABLE (*((volatile U32 *)0xE0000E00U))
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#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078U))
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#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007CU))
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#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007CU))
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#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007CU))
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/* Variables */
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extern BIT dbg_msg;
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/* Functions */
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#ifdef __USE_EXCLUSIVE_ACCESS
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#define rt_inc(p) while(__strex((__ldrex(p)+1U),p))
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#define rt_dec(p) while(__strex((__ldrex(p)-1U),p))
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#else
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#define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
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#define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
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#endif
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__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
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U32 cnt,c2;
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#ifdef __USE_EXCLUSIVE_ACCESS
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do {
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if ((cnt = __ldrex(count)) == size) {
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__clrex();
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return (cnt); }
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} while (__strex(cnt+1U, count));
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do {
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c2 = (cnt = __ldrex(first)) + 1U;
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if (c2 == size) { c2 = 0U; }
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} while (__strex(c2, first));
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#else
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__disable_irq();
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if ((cnt = *count) < size) {
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*count = (U8)(cnt+1U);
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c2 = (cnt = *first) + 1U;
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if (c2 == size) { c2 = 0U; }
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*first = (U8)c2;
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}
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__enable_irq ();
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#endif
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return (cnt);
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}
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__inline static void rt_systick_init (void) {
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NVIC_ST_RELOAD = os_trv;
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NVIC_ST_CURRENT = 0U;
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NVIC_ST_CTRL = 0x0007U;
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NVIC_SYS_PRI3 |= 0xFF000000U;
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}
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__inline static U32 rt_systick_val (void) {
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return (os_trv - NVIC_ST_CURRENT);
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}
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__inline static U32 rt_systick_ovf (void) {
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return ((NVIC_INT_CTRL >> 26) & 1U);
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}
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__inline static void rt_svc_init (void) {
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#if !defined(__TARGET_ARCH_6S_M)
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U32 sh,prigroup;
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#endif
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NVIC_SYS_PRI3 |= 0x00FF0000U;
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#if defined(__TARGET_ARCH_6S_M)
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NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000U;
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#else
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sh = 8U - __clz(~((NVIC_SYS_PRI3 << 8) & 0xFF000000U));
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prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07U);
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if (prigroup >= sh) {
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sh = prigroup + 1U;
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}
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NVIC_SYS_PRI2 = ((0xFEFFFFFFU << sh) & 0xFF000000U) | (NVIC_SYS_PRI2 & 0x00FFFFFFU);
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#endif
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}
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extern void rt_set_PSP (U32 stack);
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extern U32 rt_get_PSP (void);
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extern void os_set_env (void);
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extern void *_alloc_box (void *box_mem);
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extern U32 _free_box (void *box_mem, void *box);
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extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
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extern void rt_ret_val (P_TCB p_TCB, U32 v0);
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extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
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extern void dbg_init (void);
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extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
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extern void dbg_task_switch (U32 task_id);
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#ifdef DBG_MSG
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#define DBG_INIT() dbg_init()
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#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
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#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.next!=os_tsk.run)) \
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dbg_task_switch(task_id)
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#else
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#define DBG_INIT()
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#define DBG_TASK_NOTIFY(p_tcb,create)
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#define DBG_TASK_SWITCH(task_id)
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#endif
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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