141 lines
4.1 KiB
ArmAsm
141 lines
4.1 KiB
ArmAsm
/******************************************************************************
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* @file startup_ARMCA9.s
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* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
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* @version V1.00
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* @date 01 Nov 2017
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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MODULE ?startup_ARMCA9
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/*----------------------------------------------------------------------------
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Exception / Interrupt Handler
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*----------------------------------------------------------------------------*/
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PUBLIC Reset_Handler
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PUBWEAK Undef_Handler
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PUBWEAK SVC_Handler
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PUBWEAK PAbt_Handler
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PUBWEAK DAbt_Handler
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PUBWEAK IRQ_Handler
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PUBWEAK FIQ_Handler
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION USR_STACK:DATA:NOROOT(3)
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/*----------------------------------------------------------------------------
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Exception / Interrupt Vector Table
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*----------------------------------------------------------------------------*/
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section RESET:CODE:NOROOT(2)
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PUBLIC Vectors
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Vectors:
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LDR PC, =Reset_Handler
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LDR PC, =Undef_Handler
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LDR PC, =SVC_Handler
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LDR PC, =PAbt_Handler
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LDR PC, =DAbt_Handler
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NOP
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LDR PC, =IRQ_Handler
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LDR PC, =FIQ_Handler
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section .text:CODE:NOROOT(2)
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/*----------------------------------------------------------------------------
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Reset Handler called on controller reset
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*----------------------------------------------------------------------------*/
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EXTERN SystemInit
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EXTERN __iar_program_start
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Reset_Handler:
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// Mask interrupts
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CPSID if
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// Put any cores other than 0 to sleep
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MRC p15, 0, R0, c0, c0, 5
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ANDS R0, R0, #3
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goToSleep:
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WFINE
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BNE goToSleep
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// Reset SCTLR Settings
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MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
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BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
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BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
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BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
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BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
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BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
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MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
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ISB
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// Configure ACTLR
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MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
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ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
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MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
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// Set Vector Base Address Register (VBAR) to point to this application's vector table
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LDR R0, =Vectors
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MCR p15, 0, R0, c12, c0, 0
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// Setup Stack for each exception mode
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CPS #0x11
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LDR SP, =SFE(FIQ_STACK)
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CPS #0x12
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LDR SP, =SFE(IRQ_STACK)
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CPS #0x13
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LDR SP, =SFE(SVC_STACK)
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CPS #0x17
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LDR SP, =SFE(ABT_STACK)
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CPS #0x1B
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LDR SP, =SFE(UND_STACK)
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CPS #0x1F
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LDR SP, =SFE(USR_STACK)
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// Call SystemInit
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BL SystemInit
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// Unmask interrupts
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CPSIE if
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// Call __iar_program_start
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BL __iar_program_start
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/*----------------------------------------------------------------------------
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Default Handler for Exceptions / Interrupts
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*----------------------------------------------------------------------------*/
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Undef_Handler:
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SVC_Handler:
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PAbt_Handler:
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DAbt_Handler:
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IRQ_Handler:
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FIQ_Handler:
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Default_Handler:
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B .
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END
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