486 lines
23 KiB
ArmAsm
486 lines
23 KiB
ArmAsm
/*
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* Copyright (c) 2013-2023 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Project: CMSIS-RTOS RTX
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* Title: ARMv7-A Exception handlers
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*
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* -----------------------------------------------------------------------------
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*/
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.syntax unified
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#include "rtx_def.h"
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.equ MODE_FIQ, 0x11
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.equ MODE_IRQ, 0x12
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.equ MODE_SVC, 0x13
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.equ MODE_ABT, 0x17
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.equ MODE_UND, 0x1B
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.equ CPSR_BIT_T, 0x20
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.equ K_STATE_RUNNING, 2 // osKernelState_t::osKernelRunning
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.equ I_K_STATE_OFS, 8 // osRtxInfo.kernel.state offset
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.equ I_TICK_IRQN_OFS, 16 // osRtxInfo.tick_irqn offset
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.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
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.equ TCB_SP_FRAME, 34 // osRtxThread_t.stack_frame offset
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.equ TCB_SP_OFS, 56 // osRtxThread_t.sp offset
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.equ TCB_ZONE_OFS, 68 // osRtxThread_t.zone offset
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.section ".rodata"
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.global irqRtxLib // Non weak library reference
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irqRtxLib:
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.byte 0
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.section ".data"
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.global SVC_Active
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.global IRQ_PendSV
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IRQ_NestLevel:
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.word 0 // IRQ nesting level counter
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SVC_Active:
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.byte 0 // SVC Handler Active
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IRQ_PendSV:
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.byte 0 // Pending SVC flag
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.arm
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.section ".text"
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.align 4
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.type Undef_Handler, %function
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.global Undef_Handler
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.fnstart
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.cantunwind
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Undef_Handler:
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srsfd sp!, #MODE_UND
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push {r0-r4, r12} // Save APCS corruptible registers to UND mode stack
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mrs r0, spsr
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tst r0, #CPSR_BIT_T // Check mode
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moveq r1, #4 // R1 = 4 ARM mode
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movne r1, #2 // R1 = 2 Thumb mode
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sub r0, lr, r1
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ldreq r0, [r0] // ARM mode - R0 points to offending instruction
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beq Undef_Cont
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// Thumb instruction
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// Determine if it is a 32-bit Thumb instruction
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ldrh r0, [r0]
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mov r2, #0x1C
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cmp r2, r0, lsr #11
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bhs Undef_Cont // 16-bit Thumb instruction
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// 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction
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ldrh r2, [lr]
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orr r0, r2, r0, lsl #16
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Undef_Cont:
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mov r2, lr // Set LR to third argument
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and r12, sp, #4 // Ensure stack is 8-byte aligned
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sub sp, sp, r12 // Adjust stack
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push {r12, lr} // Store stack adjustment and dummy LR
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// R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)
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bl CUndefHandler
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pop {r12, lr} // Get stack adjustment & discard dummy LR
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add sp, sp, r12 // Unadjust stack
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ldr lr, [sp, #24] // Restore stacked LR and possibly adjust for retry
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sub lr, lr, r0
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ldr r0, [sp, #28] // Restore stacked SPSR
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msr spsr_cxsf, r0
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clrex // Clear exclusive monitor
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pop {r0-r4, r12} // Restore stacked APCS registers
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add sp, sp, #8 // Adjust SP for already-restored banked registers
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movs pc, lr
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.fnend
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.size Undef_Handler, .-Undef_Handler
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.type PAbt_Handler, %function
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.global PAbt_Handler
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.fnstart
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.cantunwind
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PAbt_Handler:
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sub lr, lr, #4 // Pre-adjust LR
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srsfd sp!, #MODE_ABT // Save LR and SPRS to ABT mode stack
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push {r0-r4, r12} // Save APCS corruptible registers to ABT mode stack
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mrc p15, 0, r0, c5, c0, 1 // IFSR
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mrc p15, 0, r1, c6, c0, 2 // IFAR
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mov r2, lr // Set LR to third argument
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and r12, sp, #4 // Ensure stack is 8-byte aligned
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sub sp, sp, r12 // Adjust stack
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push {r12, lr} // Store stack adjustment and dummy LR
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bl CPAbtHandler
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pop {r12, lr} // Get stack adjustment & discard dummy LR
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add sp, sp, r12 // Unadjust stack
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clrex // Clear exclusive monitor
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pop {r0-r4, r12} // Restore stack APCS registers
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rfefd sp! // Return from exception
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.fnend
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.size PAbt_Handler, .-PAbt_Handler
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.type DAbt_Handler, %function
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.global DAbt_Handler
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.fnstart
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.cantunwind
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DAbt_Handler:
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sub lr, lr, #8 // Pre-adjust LR
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srsfd sp!, #MODE_ABT // Save LR and SPRS to ABT mode stack
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push {r0-r4, r12} // Save APCS corruptible registers to ABT mode stack
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mrc p15, 0, r0, c5, c0, 0 // DFSR
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mrc p15, 0, r1, c6, c0, 0 // DFAR
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mov r2, lr // Set LR to third argument
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and r12, sp, #4 // Ensure stack is 8-byte aligned
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sub sp, sp, r12 // Adjust stack
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push {r12, lr} // Store stack adjustment and dummy LR
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bl CDAbtHandler
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pop {r12, lr} // Get stack adjustment & discard dummy LR
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add sp, sp, r12 // Unadjust stack
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clrex // Clear exclusive monitor
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pop {r0-r4, r12} // Restore stacked APCS registers
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rfefd sp! // Return from exception
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.fnend
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.size DAbt_Handler, .-DAbt_Handler
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.type IRQ_Handler, %function
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.global IRQ_Handler
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.fnstart
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.cantunwind
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IRQ_Handler:
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sub lr, lr, #4 // Pre-adjust LR
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srsfd sp!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack
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cps #MODE_SVC // Change to SVC mode
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push {r0-r3, r12, lr} // Save APCS corruptible registers
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ldr r0, =IRQ_NestLevel
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ldr r1, [r0]
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add r1, r1, #1 // Increment IRQ nesting level
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str r1, [r0]
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mov r3, sp // Move SP into R3
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and r3, r3, #4 // Get stack adjustment to ensure 8-byte alignment
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sub sp, sp, r3 // Adjust stack
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push {r3, r4} // Store stack adjustment(R3) and user data(R4)
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blx IRQ_GetActiveIRQ // Retrieve interrupt ID into R0
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mov r4, r0 // Move interrupt ID to R4
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blx IRQ_GetHandler // Retrieve interrupt handler address for current ID
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cmp r0, #0 // Check if handler address is 0
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beq IRQ_End // If 0, end interrupt and return
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cpsie i // Re-enable interrupts
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blx r0 // Call IRQ handler
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cpsid i // Disable interrupts
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IRQ_End:
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mov r0, r4 // Move interrupt ID to R0
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blx IRQ_EndOfInterrupt // Signal end of interrupt
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pop {r3, r4} // Restore stack adjustment(R3) and user data(R4)
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add sp, sp, r3 // Unadjust stack
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bl osRtxContextSwitch // Continue in context switcher
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ldr r0, =IRQ_NestLevel
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ldr r1, [r0]
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subs r1, r1, #1 // Decrement IRQ nesting level
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str r1, [r0]
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clrex // Clear exclusive monitor for interrupted code
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pop {r0-r3, r12, lr} // Restore stacked APCS registers
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rfefd sp! // Return from IRQ handler
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.fnend
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.size IRQ_Handler, .-IRQ_Handler
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.type SVC_Handler, %function
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.global SVC_Handler
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.fnstart
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.cantunwind
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SVC_Handler:
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srsfd sp!, #MODE_SVC // Store SPSR_svc and LR_svc onto SVC stack
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push {r12, lr}
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mrs r12, spsr // Load SPSR
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tst r12, #CPSR_BIT_T // Thumb bit set?
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ldrhne r12, [lr,#-2] // Thumb: load halfword
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bicne r12, r12, #0xFF00 // extract SVC number
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ldreq r12, [lr,#-4] // ARM: load word
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biceq r12, r12, #0xFF000000 // extract SVC number
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cmp r12, #0 // Compare SVC number
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bne SVC_User // Branch if User SVC
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push {r0-r3} // Push arguments to stack
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ldr r0, =SVC_Active
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mov r1, #1
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strb r1, [r0] // Set SVC Handler Active
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ldr r0, =IRQ_NestLevel
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ldr r1, [r0]
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add r1, r1, #1 // Increment IRQ nesting level
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str r1, [r0]
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ldr r0, =osRtxInfo
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ldr r1, [r0, #I_K_STATE_OFS] // Load RTX5 kernel state
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cmp r1, #K_STATE_RUNNING // Check osKernelRunning
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blt SVC_FuncCall // Continue if kernel is not running
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ldr r0, [r0, #I_TICK_IRQN_OFS] // Load OS Tick irqn
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blx IRQ_Disable // Disable OS Tick interrupt
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SVC_FuncCall:
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ldm sp, {r0-r3, r12} // Reload R0-R3 and R12 from stack
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cpsie i // Re-enable interrupts
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blx r12 // Branch to SVC function
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cpsid i // Disable interrupts
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str r0, [sp] // Store function return value
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ldr r0, =osRtxInfo
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ldr r1, [r0, #I_K_STATE_OFS] // Load RTX5 kernel state
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cmp r1, #K_STATE_RUNNING // Check osKernelRunning
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blt SVC_ContextCheck // Continue if kernel is not running
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ldr r0, [r0, #I_TICK_IRQN_OFS] // Load OS Tick irqn
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blx IRQ_Enable // Enable OS Tick interrupt
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SVC_ContextCheck:
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bl osRtxContextSwitch // Continue in context switcher
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ldr r0, =IRQ_NestLevel
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ldr r1, [r0]
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sub r1, r1, #1 // Decrement IRQ nesting level
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str r1, [r0]
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ldr r0, =SVC_Active
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mov r1, #0
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strb r1, [r0] // Clear SVC Handler Active
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clrex // Clear exclusive monitor
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pop {r0-r3, r12, lr} // Restore stacked APCS registers
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rfefd sp! // Return from exception
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SVC_User:
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push {r4, r5}
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ldr r5,=osRtxUserSVC // Load address of SVC table
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ldr r4,[r5] // Load SVC maximum number
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cmp r12,r4 // Check SVC number range
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bhi SVC_Done // Branch if out of range
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ldr r12,[r5,r12,lsl #2] // Load SVC Function Address
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blx r12 // Call SVC Function
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SVC_Done:
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clrex // Clear exclusive monitor
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pop {r4, r5, r12, lr}
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rfefd sp! // Return from exception
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.fnend
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.size SVC_Handler, .-SVC_Handler
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.type osRtxContextSwitch, %function
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.global osRtxContextSwitch
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.fnstart
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.cantunwind
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osRtxContextSwitch:
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push {lr}
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// Check interrupt nesting level
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ldr r0, =IRQ_NestLevel
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ldr r1, [r0] // Load IRQ nest level
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cmp r1, #1
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bne osRtxContextExit // Nesting interrupts, exit context switcher
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ldr r12, =osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
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ldm r12, {r0, r1} // Load osRtxInfo.thread.run: curr & next
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ldr r2, =IRQ_PendSV // Load address of IRQ_PendSV flag
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ldrb r3, [r2] // Load PendSV flag
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cmp r0, r1 // Check if context switch is required
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bne osRtxContextCheck // Not equal, check if context save required
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cmp r3, #1 // Compare IRQ_PendSV value
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bne osRtxContextExit // No post processing (and no context switch requested)
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osRtxContextCheck:
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str r1, [r12] // Store run.next as run.curr
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// R0 = curr, R1 = next, R2 = &IRQ_PendSV, R12 = &osRtxInfo.thread.run
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push {r0-r2, r12}
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cmp r0, #0 // Is osRtxInfo.thread.run.curr == 0
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beq osRtxPostProcess // Current deleted, skip context save
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osRtxContextSave:
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mov lr, r0 // Move &osRtxInfo.thread.run.curr to LR
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mov r0, sp // Move SP_svc into R0
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add r0, r0, #20 // Adjust SP_svc to R0 of the basic frame
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sub sp, sp, #4
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stm sp, {sp}^ // Save SP_usr to current stack
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pop {r1} // Pop SP_usr into R1
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sub r1, r1, #64 // Adjust SP_usr to R4 of the basic frame
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stmia r1!, {r4-r11} // Save R4-R11 to user stack
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ldmia r0!, {r4-r8} // Load stacked R0-R3,R12 into R4-R8
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stmia r1!, {r4-r8} // Store them to user stack
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stm r1, {lr}^ // Store LR_usr directly
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add r1, r1, #4 // Adjust user sp to PC
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ldmib r0!, {r5-r6} // Load stacked PC, CPSR
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stmia r1!, {r5-r6} // Store them to user stack
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sub r1, r1, #64 // Adjust SP_usr to stacked R4
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// Check if VFP state need to be saved
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mrc p15, 0, r2, c1, c0, 2 // VFP/NEON access enabled? (CPACR)
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and r2, r2, #0x00F00000
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cmp r2, #0x00F00000
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bne osRtxContextSaveSP // Continue, no VFP
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vmrs r2, fpscr
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stmdb r1!, {r2,r12} // Push FPSCR, maintain 8-byte alignment
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vstmdb r1!, {d0-d15} // Save D0-D15
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#if defined(__ARM_NEON) && (__ARM_NEON == 1)
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vstmdb r1!, {d16-d31} // Save D16-D31
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#endif
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ldrb r2, [lr, #TCB_SP_FRAME] // Load osRtxInfo.thread.run.curr frame info
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#if defined(__ARM_NEON) && (__ARM_NEON == 1)
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orr r2, r2, #4 // NEON state
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#else
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orr r2, r2, #2 // VFP state
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#endif
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strb r2, [lr, #TCB_SP_FRAME] // Store VFP/NEON state
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osRtxContextSaveSP:
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str r1, [lr, #TCB_SP_OFS] // Store user sp to osRtxInfo.thread.run.curr
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osRtxPostProcess:
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// RTX IRQ post processing check
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pop {r8-r11} // Pop R8 = curr, R9 = next, R10 = &IRQ_PendSV, R11 = &osRtxInfo.thread.run
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ldrb r0, [r10] // Load PendSV flag
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cmp r0, #1 // Compare PendSV value
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bne osRtxContextRestore // Skip post processing if not pending
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mov r4, sp // Move SP_svc into R4
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and r4, r4, #4 // Get stack adjustment to ensure 8-byte alignment
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sub sp, sp, r4 // Adjust stack
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// Disable OS Tick
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ldr r5, =osRtxInfo // Load address of osRtxInfo
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ldr r5, [r5, #I_TICK_IRQN_OFS] // Load OS Tick irqn
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mov r0, r5 // Set it as function parameter
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blx IRQ_Disable // Disable OS Tick interrupt
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mov r6, #0 // Set PendSV clear value
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b osRtxPendCheck
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osRtxPendExec:
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strb r6, [r10] // Clear PendSV flag
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cpsie i // Re-enable interrupts
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blx osRtxPendSV_Handler // Post process pending objects
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cpsid i // Disable interrupts
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osRtxPendCheck:
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ldr r9, [r11, #4] // Load osRtxInfo.thread.run.next
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str r9, [r11] // Store run.next as run.curr
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ldrb r0, [r10] // Load PendSV flag
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cmp r0, #1 // Compare PendSV value
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beq osRtxPendExec // Branch to PendExec if PendSV is set
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// Re-enable OS Tick
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mov r0, r5 // Restore irqn as function parameter
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blx IRQ_Enable // Enable OS Tick interrupt
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add sp, sp, r4 // Restore stack adjustment
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osRtxContextRestore:
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#ifdef RTX_EXECUTION_ZONE
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ldrb r0, [r9, #TCB_ZONE_OFS] // Load osRtxInfo.thread.run.next: zone
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cmp r8, #0
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beq osRtxZoneSetup // Branch if running thread is deleted
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ldrb r1, [r8, #TCB_ZONE_OFS] // Load osRtxInfo.thread.run.curr: zone
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cmp r0, r1 // Check if next:zone == curr:zone
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beq osRtxContextRestoreFrame // Branch if zone has not changed
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osRtxZoneSetup:
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bl osZoneSetup_Callback // Setup zone for next thread
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#endif
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osRtxContextRestoreFrame:
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ldr lr, [r9, #TCB_SP_OFS] // Load next osRtxThread_t.sp
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ldrb r2, [r9, #TCB_SP_FRAME] // Load next osRtxThread_t.stack_frame
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ands r2, r2, #0x6 // Check stack frame for VFP context
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mrc p15, 0, r2, c1, c0, 2 // Read CPACR
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andeq r2, r2, #0xFF0FFFFF // VFP/NEON state not stacked, disable VFP/NEON
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orrne r2, r2, #0x00F00000 // VFP/NEON state is stacked, enable VFP/NEON
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mcr p15, 0, r2, c1, c0, 2 // Write CPACR
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beq osRtxContextRestoreRegs // No VFP
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isb // Sync if VFP was enabled
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#if defined(__ARM_NEON) && (__ARM_NEON == 1)
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vldmia lr!, {d16-d31} // Restore D16-D31
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#endif
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vldmia lr!, {d0-d15} // Restore D0-D15
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ldr r2, [lr]
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vmsr fpscr, r2 // Restore FPSCR
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add lr, lr, #8 // Adjust sp pointer to R4
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osRtxContextRestoreRegs:
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ldmia lr!, {r4-r11} // Restore R4-R11
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add r12, lr, #32 // Adjust sp and save it into R12
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push {r12} // Push sp onto stack
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ldm sp, {sp}^ // Restore SP_usr directly
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add sp, sp, #4 // Adjust SP_svc
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ldmia lr!, {r0-r3, r12} // Load user registers R0-R3,R12
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stmib sp!, {r0-r3, r12} // Store them to SP_svc
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ldm lr, {lr}^ // Restore LR_usr directly
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ldmib lr!, {r0-r1} // Load user registers PC,CPSR
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add sp, sp, #4
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stmib sp!, {r0-r1} // Store them to SP_svc
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sub sp, sp, #32 // Adjust SP_svc to stacked LR
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osRtxContextExit:
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pop {pc} // Return
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.fnend
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.size osRtxContextSwitch, .-osRtxContextSwitch
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.end
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